873991AY-147LF datasheet(11/20 Pages) IDT

Part #	873991AY-147LF

Description	Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

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Manufacturer	IDT [Integrated Device Technology]

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REVISION B 8/25/15

873991-147 DATA SHEET

11

LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

CLOCK GENERATOR

FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVDS DRIVER

3.3V

R1

50

R3

50

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

R2

50

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

R3

125

R2

84

Zo = 50 Ohm

3.3V

R4

125

LVPECL

R1

84

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both V

SWING

and V

OH

must meet the V

PP

and

V

CMR

input requirements. Figures 4A to 4F show interface examples

for the HiPerClockS CLK/nCLK input driven by the most common

driver types.The input interfaces suggested here are examples only.

FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY AN IDT OPEN EMITTER

HIPERCLOCKS LVHSTL DRIVER

Please consult with the vendor of the driver component to conﬁrm

the driver termination requirements. For example in Figure 4A, the

input termination applies for IDT HiPerClockS open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor,

use their termination recommendation.

1.8V

R2

50

Input

LVHSTL Driver

ICS

HiPerClockS

R1

50

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

R1

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V HCSL DRIVER

FIGURE 4F.

HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 2.5V SSTL DRIVER

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873991AY-147LF Datasheet(PDF) 11 Page - Integrated Device Technology

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