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TUSB544I Datasheet(PDF) 4 Page - Texas Instruments |
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TUSB544I Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 60 page  4 TUSB544 SLLSEZ0B – APRIL 2017 – REVISED MAY 2017 www.ti.com Product Folder Links: TUSB544 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME 11 DIR1 2 Level I/O This pin along with DIR0 sets the data path signal direction format. Refer to Table 4 for signal direction formats. 12 UTX2p Diff I/O Differential positive input/output for upstream facing TX2 port. 13 UTX2n Diff I/O Differential negative input/output for upstream facing TX2 port. 14 VIO_SEL 4 Level I/O This pin selects I/O voltage levels for the GPIO configuration pins and the I2C interface: 0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default) R = 3.3-V configuration I/O voltage, 1.8-V I2C interface F = 1.8-V configuration I/O voltage, 3.3-V I2C interface 1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface. 15 UTX1n Diff I/O Differential negative input/output for upstream facing TX1 port. 16 UTX1p Diff I/O Differential positive input/output for upstream facing TX1 port. 17 I2C_EN 4 Level I I2C Programming or Pin Strap Programming Select. 0 = GPIO Mode (I2C disabled) R = TI Test Mode (I2C enabled) F = GPIO Mode, AUX Snoop Disabled (I2C disabled) 1 = I2C enabled. 18 URX1n Diff I/O Differential negative input/output for upstream facing RX1 port. 19 URX1p Diff I/O Differential positive input/output for upstream facing RX1 port. 20 VCC P 3.3V Power Supply 21 FLIP/SCL 2 Level I (Failsafe) When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. 22 CTL0/SDA 2 Level I (Failsafe) When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. 23 CTL1 2 Level I (PD) DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality. Otherwise DisplayPort functionality is enabled and disabled through I2C registers. L = DisplayPort Disabled. H = DisplayPort Enabled. When I2C_EN = 0, this pin is not used by device. 24 AUXp I/O, CMOS AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between the AC coupling capacitor and the AUXp pin if the TUSB544 is used on the DisplayPort source side, or a 1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB544 is used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB544 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug. 25 AUXn I/O, CMOS AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXn pin if the TUSB544 is used on the DisplayPort source side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB544 is used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB544 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug. 26 SBU2 I/O, CMOS SBU2. When the TUSB544 is used on the DisplayPort source side, this pin should be DC coupled to the SBU2 pin of the Type-C receptacle. When the TUSB544 is used on the DisplayPort sink side, this pin should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also recommended. 27 SBU1 I/O, CMOS SBU1. When the TUSB544 is used on the DisplayPort source side, this pin should be DC coupled to the SBU1 pin of the Type-C receptacle. When the TUSB544 is used on the DisplayPort sink side, this pin should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also recommended. 28 VCC P 3.3V Power Supply 29 DEQ1 4 Level I This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2, DTX1, DTX2 receivers. Up to 11 dB of EQ available. 30 DRX1p Diff I/O Differential positive input/output for downstream facing RX1 port. 31 DRX1n Diff I/O Differential negative input/output for downstream facing RX1 port. 32 HPDIN 2 Level I (PD) When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. 33 DTX1p Diff I/O Differential positive input/output for downstream facing TX1 port. 34 DTX1n Diff I/O Differential negative input/output for downstream facing TX1 port. 35 UEQ0/A0 4 Level I This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. Up to 9.4 dB of EQ available. When I2C_EN !=0, this pin will also set TUSB544’s I2C address. Refer to Table 10. 36 DTX2n Diff I/O Differential negative input/output for downstream facing TX2 port. |
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