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TPS24713DGS Datasheet(PDF) 3 Page - Texas Instruments |
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TPS24713DGS Datasheet(HTML) 3 Page - Texas Instruments |
3 / 38 page 3 TPS24710, TPS24711 TPS24712, TPS24713 www.ti.com SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015 Product Folder Links: TPS24710 TPS24711 TPS24712 TPS24713 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Changes from Revision D (November 2013) to Revision E Page • Reverted Equation 2 in rev E back to rev C ......................................................................................................................... 15 • Reverted Equation 9 in rev E back to rev C ......................................................................................................................... 27 Changes from Revision C (May 2011) to Revision D Page • Added Note 1 to the Supply Current Conditions statement ................................................................................................... 6 • Added Note 1 to Fast-turnoff delay ....................................................................................................................................... 7 • Changed the Functional Block Diagram From: VCC = 6 V to VCC = 5.9 V at the Gate Comparator ..................................... 13 • Changed text in the GATE section From: "Timer Activation Voltage (6 V for VVCC = 12 V)." To: "Timer Activation Voltage (5.9 V for VVCC = 12 V).".......................................................................................................................................... 14 • Changed the first paragraph of the Inrush Operation section .............................................................................................. 18 • Added text and new Equation 10 ......................................................................................................................................... 27 • Changed text prior to Equation 12 From: "6 V (for VVCC = 12 V)" To: "5.9 V (for VVCC = 12 V)".......................................... 28 • Changed the text following Equation 12............................................................................................................................... 28 • Changed text following Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode From: "Set PLIM to a value greater than VVCC × ICHG" To: "Choose ICHG < PLIM / VVCC" .................................................................................. 29 • Changed Equation 15 From: – CISS To: – CRS (this equation deleted by Revision F).......................................................... 29 Changes from Revision B (April 2011) to Revision C Page • Changed in PGb: from: 140V/340mV, to:170mV / 240mV .................................................................................................. 15 • Changed in Equation 8: rDS(on) to RSENSE .............................................................................................................................. 27 Changes from Revision A (March 2011) to Revision B Page • Corrected voltage values shown in Figure 26 ...................................................................................................................... 13 |
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