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50 mV

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S

11

TPS2490, TPS2491

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SLVS503E – NOVEMBER 2003 – REVISED FEBRUARY 2017

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7.3 Feature Description

7.3.1

VCC

This pin is associated with three functions:

1. Biasing power to the integrated circuit

2. Input to power on reset (POR) and undervoltage lockout (UVLO) functions

The voltage must exceed the POR (about 6 V for approximately 400 µs) and the internal UVLO (about 8 V)

eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR are

active.

7.3.2 SENSE

and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses

current limit is set by Equation 1:

(1)

difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by

connecting SENSE to VCC.

7.3.3 GATE

Provides the high side (above VCC) gate drive for Q1. It is controlled by the internal gate drive amplifier, which

provides a pull-up of 22 µA from an internal charge pump and a strong pulldown to ground of 75 mA (minimum).

The pulldown current is a nonlinear function of the amplifier overdrive; it provides small drive for small overloads,

but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut Q1 off when

EN or UVLO cause this to happen. An internal clamp protects the gate of Q1 (to OUT) and generally eliminates

A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile

without affecting the amplifier stability. Add a series resistor of about 1 k

Ω to the gate capacitor to maintain the

gate clamping and current limit response time. Adding capacitance across Q1 gate to source requires some

series damping resistance to avoid high-frequency oscillations.

7.3.4 OUT

below ground, connect a clamp (or freewheel) diode such as an S1B from OUT (cathode) to GND (anode).

7.3.5 EN

The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds

have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by

R1/R2 in the Figure 17 circuit, or it can be tied to VCC to always enable the TPS249x. The hysteresis associated

with the internal comparator makes this a stable method of detecting a low input condition and shutting the

downstream circuits off. A TPS2490 that has latched off can be reset by cycling EN below its negative threshold

and back high.