UCC28060

TERMINAL FUNCTIONS (continued)

TERMINAL

DESCRIPTION

NAME

NO.

I/O

Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time for

channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage

constant during the phase management transient. The PHB thresholds change with line range for the

PHB

4

I

best efficiency when PHB is connected to COMP. PHB can also be driven by external logic signals to

allow customized phase management. To disable phase management, connect the PHB pin to the

VREF pin.

PWM enable logic output: This open-drain output goes low when HVSEN is within the HVSEN good

PWMCNTL

9

O

region and the ZCDA and ZCDB inputs are switching correctly if operating in two-phase mode (see PHB

Pin). Otherwise, PWMCNTL is high impedance.

Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the

TSET

3

I

on-time versus COMP voltage and the minimum period at the gate drive outputs.

Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect

VCC

12

—

a 0.1-

µF ceramic bypass capacitor from this pin to PGND. This supply powers all circuits in the device

and must be capable of delivering 6 mA dc plus the transient power MOSFET gate charging current.

Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified

input power mains. This input senses input voltage range to set the ramp rate and senses brownout.

Input voltage range changes when the peak voltage on VINAC becomes and stays below the range

change threshold for the range change filter time or the peak voltage on VINAC becomes above the

VINAC

7

I

range change threshold. When the voltage on VINAC remains below the brownout threshold for more

than the brownout filter time, the device enters a brownout mode and both output drives are disabled.

Select the input voltage divider ratio for the desired brownout threshold and power line range. Select the

divider impedance for the desired brownout hysteresis.

Voltage reference output: Connect a 0.1-

µF ceramic bypass capacitor from this pin to AGND.

VREF

15

O

This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.

Output dc voltage sense: Connect this pin to a voltage divider across the output of the power

converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the

desired output voltage. Connect the ground side of this divider to ground through a separate short trace

VSENSE

2

I

for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drain

logic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduce

VCC current. If VSENSE is disconnected, open-loop protection provides an internal current source to

pull VSENSE low, turning off the gate drivers.

Zero current detection inputs: These inputs expect to see a negative edge when the inductor current

in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupled

ZCDA

16

I

through a series resistor that limits the clamping current to less than ±3 mA. Connect these pins through

a current limiting resistor to the zero crossing detection windings of the appropriate boost

inductor. The inductor winding must be connected so that this voltage drops when inductor current

decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling

ZCDB

1

I

threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off,

the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for another

falling ZCD edge.

8

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