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Z32F06410AKS Datasheet(PDF) 9 Page - Zilog, Inc. |
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Z32F06410AKS Datasheet(HTML) 9 Page - Zilog, Inc. |
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9 / 205 page  Z32F0641 Product Specification Overview PS034404-0417 PRELIMINARY 6 Functional Description The following section provides an overview of the features of the Z32F0641 microcontroller. ARM Cortex-M3 ARM-powered Cortex-M3 core based on ARMv7M architecture, which is optimized for small-size and low-power systems. On core system timer (SYSTICK) provides a simple 24-bit timer that enables easy management of system operations Thumb-compatible Thumb-2 only instruction set processor core makes code high-density Hardware division and single-cycle multiplication Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling JTAG and SWD debugging features Maximum 48 MHz operating frequency with zero wait execution Nested Vector-Interrupt Controller (NVIC) The ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core handles all internal and external exceptions. When an interrupt condition is detected, the processor state is automatically stored to the stack and automatically restored from the stack at the end of interrupt service routine. The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which allows for back-to-back interrupts to be performed without the overhead of state saving and restoring 64 KB Internal Code Flash Memory The Z32F0641 MCU provides internal 64 KB code Flash memory and its controller, which is sufficient to program the motor algorithm and control the system. Self-programming is available and ISP and JTAG programming is also supported in boot or debugging mode. Instruction and data cache buffer are present and overcome the low-bandwidth Flash memory. The CPU can execute from Flash memory with zero wait state up to 48 MHz bus frequency. 8 KB 0-wait Internal SRAM On chip 8 KB 0-wait SRAM can be used for working memory space and program code can be loaded on this SRAM Boot Logic Smart boot logic supports Flash programming. The Z32F0641 MCU can be accessed by an external boot pin; UART and SPI programming are available in Boot Mode System Control Unit The System Control Unit (SCU) block manages internal power, clock, reset, and Operation Mode. The SCU also controls analog blocks (Oscillator Block, VDC and LVD) 32-bit Watchdog Timer The Watchdog Timer (WDT) performs the system monitoring function. The WDT generates an internal reset or interrupt if the system is in abnormal state Multi-purpose 16-bit Timer Six-channel 16-bit general purpose timers support the following functions o Periodic timer mode o Counter mode o PWM mode o Capture mode |
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