MARCH 10, 2017

11

5-OUTPUT 1.8V HCSL FANOUT BUFFER

9DBV0531 DATASHEET

SMBus Table: Output Enable Register

1

Byte 0

Name

Control Function

Type

0

1

Default

Bit 7

1

Bit 6

DIF OE3

Output Enable

RW

Low/Low

OE# pin control

1

Bit 5

DIF OE2

Output Enable

RW

Low/Low

OE# pin control

1

Bit 4

1

Bit 3

DIF OE1

Output Enable

RW

Low/Low

OE# pin control

1

Bit 2

1

Bit 1

DIF OE0

Output Enable

RW

Low/Low

OE# pin control

1

Bit 0

1

1. A low on these bits will overide the OE# pin and force the differential output Low/Low

SMBus Table: PLL Operating Mode and Output Amplitude Control Register

Byte 1

Name

Control Function

Type

0

1

Default

Bit 7

0

Bit 6

1

Bit 5

DIF OE4

Output Enable

RW

Low/Low

OE# pin control

1

Bit 4

0

Bit 3

1

Bit 2

1

Bit 1

AMPLITUDE 1

RW

00 = 0.6V

01 = 0.7V

1

Bit 0

AMPLITUDE 0

RW

10= 0.8V

11 = 0.9V

0

1. A low on the DIF OE bit will overide the OE# pin and force the differential output Low/Low

SMBus Table: DIF Slew Rate Control Register

Byte 2

Name

Control Function

Type

0

1

Default

Bit 7

1

Bit 6

SLEWRATESEL DIF3

Slew Rate Selection

RW

Slow setting

Fast setting

1

Bit 5

SLEWRATESEL DIF2

Slew Rate Selection

RW

Slow setting

Fast setting

1

Bit 4

1

Bit 3

SLEWRATESEL DIF1

Slew Rate Selection

RW

Slow setting

Fast setting

1

Bit 2

1

Bit 1

SLEWRATESEL DIF0

Slew Rate Selection

RW

Slow setting

Fast setting

1

Bit 0

1

SMBus Table: DIF Slew Rate Control Register

Byte 3

Name

Control Function

Type

0

1

Default

Bit 7

1

Bit 6

1

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

1

Bit 1

1

Bit 0

SLEWRATESEL DIF4

Adjust Slew Rate of DIF4

RW

Slow setting

Fast setting

1

Byte 4 is Reserved and reads back 'hFF

Reserved

Controls Output Amplitude

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved