Electronic Components Datasheet Search |
|
9DBL0851BKILFT Datasheet(PDF) 1 Page - Integrated Device Technology |
|
9DBL0851BKILFT Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 19 page DATASHEET 9DBL0841 / 9DBL0851 FEBRUARY 9, 2017 1 ©2017 Integrated Device Technology, Inc. 8-output 3.3V PCIe Zero-Delay Buffer 9DBL0841 / 9DBL0851 Description The 9DBL0841 / 9DBL0851 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL0841 / 9DBL0851 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL08P1 can be factory programmed with a user-defined power up default SMBus configuration. Recommended Application PCIe Gen1-4 clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features • 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs • 9DBL0841 default ZOUT = 100 • 9DBL0851 default ZOUT = 85 • 9DBL08P1 factory programmable defaults • Easy AC-coupling to other logic families, see IDT application note AN-891 Key Specifications • PCIe Gen1-2-3-4 CC compliant in ZDB mode • PCIe Gen2 SRIS compliant in ZDB mode • Supports PCIe Gen2-3 SRIS in fan-out mode • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew < 50ps • Bypass mode additive phase jitter is 0 ps typical rms for PCIe • Bypass mode additive phase jitter 160fs rms typ. @ 156.25M (1.5M to 10M) Features/Benefits • Direct connection to 100 (0841) or 85 (0851) transmission lines; saves 32 resistors compared to standard PCIe devices • 211mW typical power consumption (PLL mode@3.3V); eliminates thermal concerns • VDDIO allows 35% power savings at optional 1.05V; maximum power savings • SMBus-selectable features allows optimization to customer requirements: • control input polarity • control input pull up/downs • slew rate for each output • differential output amplitude • output impedance for each output • 50, 100, 125MHz operating frequency • Customer defined SMBus power up default can be programmed into P1 device; allows exact optimization to customer requirements • OE# pins; support DIF power management • HCSL-compatible differential input; can be driven by common clock sources • Spread Spectrum tolerant; allows reduction of EMI • Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application • Outputs blocked until PLL is locked; clean system start-up • Device contains default configuration; SMBus interface not required for device operation • Three selectable SMBus addresses; multiple devices can easily share an SMBus segment • Space saving 48-pin 6x6mm VFQFPN; minimal board space Block Diagram Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis. XIN/CLKIN_25 X2 CONTROL LOGIC vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SS Capable PLL OSC REF3.3 vOE(7:0)# SCLK_3.3 vSADR DIF0 DIF1 DIF2 DIF3 DIF4 DIF5 DIF6 DIF7 |
Similar Part No. - 9DBL0851BKILFT |
|
Similar Description - 9DBL0851BKILFT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |