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9DBU0541AKLFT Datasheet(PDF) 10 Page - Integrated Device Technology

Part # 9DBU0541AKLFT
Description  5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9DBU0541AKLFT Datasheet(HTML) 10 Page - Integrated Device Technology

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5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
10
MARCH 9, 2017
9DBU0541 DATASHEET
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a stop bit
Note: SMBus Address is Latched on SADR pin.
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
TstarT bit
Slave Address
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
O
O
O
O
O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
TstarT bit
Slave Address
WR
WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address
RD
ReaD
ACK
Data Byte Count=X
ACK
Beginning Byte N
ACK
O
O
O
O
O
O
Byte N + X - 1
N
Not acknowledge
PstoP bit


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