2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

2

FEBRUARY 8, 2017

9DBL0242 / 9DBL0252 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

PLL Operating Mode

24 23 22 21 20 19

FB_DNC 1

18 DIF1#

FB_DNC# 2

17 DIF1

VDDR3.3 3

16 VDDA3.3

CLK_IN 4

15 vOE0#

CLK_IN# 5

14 DIF0#

GNDDIG 6

13 DIF0

7

8

9 101112

9DBL0242/52/P2

connect epad to

GND

v prefix indicates internal 120KOhm pull down

resistor

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND

pull down resistor (biased to VDD/2)

SADR

Address

0

1101011

M

1101100

1

1101101

Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition

from 2.1V to 3.135V in <300usec.

+

Read/Write bit

State of SADR on first application of

CKPWRGD_PD#

x

x

x

True O/P

Comp. O/P

0X

X

X

Off

1

Running

1

0

Running

Running

1

Running

1

1

1

Running

0

X

1. The output state is set by B11[1:0] (Low/Low default)

2. Input polarities defined as default values for xx41/xx51 devices.

PLL

3. If Bypass mode is selected, the PLL will be off, and outputs will be running.

CKPWRGD_PD#

CLK_IN

SMBus

OE bit

OEx# Pin

DIFx/DIFx#

VDD

GND

325

86

10,21

25

16

25

PLL Analog

Description

Pin Number

Input receiver analog

Digital Power

DIF outputs

HiBW_BypM_LoBW#

MODE

Byte1 [7:6]

Readback

Byte1 [4:3]

Control

0

PLL Lo BW

00

00

MBypass

01

01

1

PLL Hi BW

11

11