6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

2

FEBRUARY 8, 2017

9DBL0641 / 9DBL0651 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

PLL Operating Mode

40 39 38 37 36 35 34 33 32 31

vSADR_tri 130 NC

^vHIBW_BYPM_LOBW# 229 vOE3#

FB_DNC 328 DIF3#

FB_DNC# 427 DIF3

VDDR3.3 526 VDDIO

CLK_IN 625 VDDA3.3

CLK_IN# 724 vOE2#

GNDDIG 823 DIF2#

SCLK_3.3 922 DIF2

SDATA_3.3 10

21 vOE1#

11 12 13 14 15 16 17 18 19 20

9DBL0641/51/P1

epad is GND

40-VFQFPN, 5mm x 5mm 0.4mm pin pitch

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)

v prefix indicates internal 120KOhm pull down resistor

SADR

Address

0

1101011

M

1101100

1

1101101

x

x

State of SADR on first application of

CKPWRGD_PD#

+

Read/Write bit

x

Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition

from 2.1V to 3.135V in <300usec.

True O/P

Comp. O/P

0X

X

X

Off

1

Running

0

X

1

Running

1

0

Running

Running

1

Running

1

1

1. The output state is set by B11[1:0] (Low/Low default)

PLL

2. If Bypass mode is selected, the PLL will be off, and outputs will be running.

CKPWRGD_PD#

CLK_IN

SMBus

OEx bit

OEx# Pin

DIFx

Pin Number

VDD

VDDIO

GND

541

Input

receiver

analog

11

8

Digital Power

16, 31

12,17,26,32,

39

41

DIF outputs,

Logic

25

41

PLL Analog

Description

HiBW_BypM_LoBW#

MODE

Byte1 [7:6]

Readback

Byte1 [4:3]

Control

0

PLL Lo BW

00

00

MBypass

01

01

1

PLL Hi BW

11

11