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5P49V5935 Datasheet(PDF) 8 Page - Integrated Device Technology |
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5P49V5935 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 33 page PROGRAMMABLE CLOCK GENERATOR 8 MARCH 10, 2017 5P49V5935 DATASHEET Table 6: I2C Bus DC Characteristics Table 7: I2C Bus AC Characteristics Note 1: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 2: I2C inputs are 5V tolerant. Symbol Parameter Conditions Min Typ Max Unit VIH Input HIGH Level For SEL1/SDA pin and SEL0/SCL pin. 0.7xVDDD 5.5 2 V VIL Input LOW Level For SEL1/SDA pin and SEL0/SCL pin. GND-0.3 0.3xVDDD V VHYS Hysteresis of Inputs 0.05xVDDD V IIN Input Leakage Current -1 30 µA VOL Output LOW Voltage IOL = 3mA 0.4 V Symbol Parameter Min Typ Max Unit FSCLK Serial Clock Frequency (SCL) 10 400 kHz tBUF Bus free time between STOP and START 1.3 µs tSU:START Setup Time, START 0.6 µs tHD:START Hold Time, START 0.6 µs tSU:DATA Setup Time, data input (SDA) 0.1 µs tHD:DATA Hold Time, data input (SDA) 1 0 µs tOVD Output data valid from clock 0.9 µs CB Capacitive Load for Each Bus Line 400 pF tR Rise Time, data and clock (SDA, SCL) 20 + 0.1xCB 300 ns tF Fall Time, data and clock (SDA, SCL) 20 + 0.1xCB 300 ns tHIGH HIGH Time, clock (SCL) 0.6 µs tLOW LOW Time, clock (SCL) 1.3 µs tSU:STOP Setup Time, STOP 0.6 µs |
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