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EFR32FG1 Datasheet(PDF) 10 Page - Silicon Laboratories |
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EFR32FG1 Datasheet(HTML) 10 Page - Silicon Laboratories |
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10 / 101 page  3.9.3 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 MSamples/s. The output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential. 3.9.4 Digital to Analog Current Converter (IDAC) The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC input pin for capacitive sensing. The current is programmable between 0.05 µA and 64 µA with several ranges with various step sizes. 3.10 Reset Management Unit (RMU) The RMU is responsible for handling reset of the EFR32FG1. A wide range of reset sources are available, including several power supply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset. 3.11 Core and Memory 3.11.1 Processor Core The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system: • ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz • Memory Protection Unit (MPU) supporting up to 8 memory segments • Up to 256 KB flash program memory • Up to 32 KB RAM data memory • Configuration and event handling of all modules • 2-pin Serial-Wire debug interface 3.11.2 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in en- ergy modes EM0 Active and EM1 Sleep. 3.11.3 Linked Direct Memory Access Controller (LDMA) The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag- ed, enabling sophisticated operations to be implemented. EFR32FG1 Flex Gecko Proprietary Protocol SoCFamily Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.9 | 9 |
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