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SPC56EL70XX Datasheet(PDF) 10 Page - STMicroelectronics |
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SPC56EL70XX Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 15 page Functional problems SPC56EL70xx, SPC564L70xx 10/15 DocID023968 Rev 4 1.13 e7322: FlexCAN: Bus Off Interrupt bit is erroneously asserted when soft reset is performed while Description: Under normal operation, when FlexCAN enters in Bus Off state, a Bus Off Interrupt is issued to the CPU if the Bus Off Mask bit (CTRL[BOFF_MSK]) in the Control Register is set. In consequence, the CPU services the interrupt and clears the ESR[BOFF_INT] flag in the Error and Status Register to turn off the Bus Off Interrupt. In continuation, if the CPU performs a soft reset after servicing the bus off interrupt request, by either requesting a global soft reset or by asserting the MCR[SOFT_RST] bit in the Module Configuration Register, once MCR[SOFT_RST] bit transitions from 1 to 0 to acknowledge the soft reset completion, the ESR[BOFF_INT] flag (and therefore the Bus Off Interrupt) is re-asserted. The defect under consideration is the erroneous value of Bus Off flag after soft reset under the scenario described in the previous paragraph. The Fault Confinement State (ESR[FLT_CONF] bit field in the Error and Status Register) changes from 0b11 to 0b00 by the soft reset, but gets back to 0b11 again for a short period, resuming after certain time to the expected Error Active state (0b00). However, this late correct state does not reflect the correct ESR[BOFF_INT] flag which stays in a wrong value and in consequence may trigger a new interrupt service. Workaround: To prevent the occurrence of the erroneous Bus Off flag (and eventual Bus Off Interrupt) the following soft reset procedure must be used: 1. Clear CTRL[BOFF_MSK] bit in the Control Register (optional step in case the Bus Off Interrupt is enabled). 2. Set MCR[SOFT_RST] bit in the Module Configuration Register. 3. Poll MCR[SOFT_RST] bit in the Module Configuration Register until this bit is cleared. 4. Wait for 4 peripheral clocks. 5. Poll ESR[FLTCONF] bit in the Error and Status Register until this field is equal to 0b00. 6. Write "1" to clear the ESR[BOFF_INT] bit in the Error and Status Register. 7. Set CTRL[BOFF_MSK] bit in the Control Register (optional step in case the Bus Off Interrupt is enabled). 1.14 e7352: DSPI: reserved bits in slave CTAR are writable Description: When the Deserial/Serial Peripheral Interface (DSPI) module is operating in slave mode (the Master [MSTR] bit of the DSPI Module Configuration Register [DSPIx_MCR] is cleared), bits 10 to 31 (31 = least significant bit) of the Clock and Transfer Attributes Registers (DSPIx_CTARx) should be read only (and always read 0). However, these bits are writable, but setting any of these bits to a 1 does not change the operation of the module. Workaround: There are two possible workarounds. Workaround 1: Always write zeros to the reserved bits of the DSPIx_CTARn_SLAVE (when operating in slave mode). Workaround 2: Mask the reserved bits of DSPIx_CTARn_SLAVE when reading the register in slave mode. |
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