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TMS320F28069PZPQ Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320F28069PZPQ Datasheet(HTML) 9 Page - Texas Instruments |
9 / 177 page 40 39 38 37 36 35 34 33 32 31 30 29 28 27 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 26 25 24 23 22 21 GPIO26/ECAP3/SPICLKB/USB0DP GPIO27/HRCAP2/SPISTEB/USB0DM V DDIO V SS V DD GPIO3/EPWM2B/SPISOMIA/COMP2OUT GPIO2/EPWM2A GPIO1/EPWM1B/COMP1OUT GPIO0/EPWM1A GPIO15/ECAP2/SCIRXDB/SPISTEB VREGENZ V DD V SS V DDIO GPIO13/ /SPISOMIB TZ2 GPIO14/ /SCITXDB/SPICLKB TZ3 GPIO24/ECAP1/SPISIMOB GPIO22/EQEP1S/MCLKXA/SCITXDB GPIO32/SDAA/EPWMSYNCI/ADCSOCAO GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO29/SCITXDA/SCLA/TZ3 GPIO12/ /SCITXDA/SPISIMOB TZ1 TEST2 V DD3VFL V SS GPIO9/EPWM5B/SCITXDB/ECAP3 GPIO28/SCIRXDA/SDAA/TZ2 GPIO30/CANRXA/EPWM7A GPIO31/CANTXA/EPWM8A GPIO25/ECAP2/SPISOMIB V DD V SS V DDIO ADCINB6/COMP3B/AIO14 ADCINB5 ADCINB4/COMP2B/AIO12 ADCINB2/COMP1B/AIO10 ADCINB1 ADCINB0 V , V REFLO SSA 9 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Terminal Configuration and Functions Copyright © 2010–2016, Texas Instruments Incorporated 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure 4-1 shows the pin assignments on the 80-pin PN and PFP packages. Figure 4-2 shows the pin assignments on the 100-pin PZ and PZP packages. A. Pin 19: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another. Pin 21: VREFLO is always connected to VSSA on the 80-pin PN and PFP devices. B. The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must be connected to the ground plane of the PCB. It should not be left unconnected. For more details, see the PowerPAD™ Thermally Enhanced Package Application Report (SLMA002). Figure 4-1. 80-Pin PN and PFP Packages (Top View) |
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