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TMS320DM6435ZDU6 Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320DM6435ZDU6 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 252 page  Revision History TMS320DM6435 Digital Media Processor SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS344B device-specific data manual to make it an SPRS344C revision. This data manual revision history highlights the technical changes made to the SPRS344B device-specific data manual to make it an SPRS344C revision. Scope: Applicable updates to the TMS320DM643x DMP, specifically relating to the TMS320DM6435 device, have been incorporated. • Added 660- and 700-MHz C64x+™ device speeds. • Added designators for low-power (-L) devices. SEE ADDITIONS/MODIFICATIONS/DELETIONS Global • Updated/Changed signal name from "C_WE" to "C_WE" • Updated/Changed signal name from "C_WEN" to "C_WE" Section 1.1 Added "5280, 5600 MIPS" to "High-Performance Digital Signal Processor (DM6435)" bullet Section 1.2 • In first paragraph, updated/changed the following: – First sentence from "With performance up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz..." to "With performance up to 5600 million instructions per second (MIPS) with a clock rate of 700 MHz..." – Fifth sentence from "The DSP core can produce...for a total of 2400 million MACs per second...or a total of 4800 MMACS."to "The DSP core can produce...for a total of 2800 million MACs per second...or a total of 5600 MMACS." Section 2.6 Table 2-19, Multichannel Audio Serial Port (McASP0) Terminal Functions: • Updated/Changed AFSR0/DR0/GP[100] pin description from "... frame synchronization AFSX0..." to "...frame synchronization AFSR0..." • Updated/Changed AFSX0/DX1/GP[107] pin description from "...frame synchronization AFSR0..." to "...frame synchronization AFSX0..." Section 2.8 Updated/Changed Figure 2-10, Device Nomenclature, to reflect new device speeds and low-power designator (-L suffix). Section 5 Added footnote to Section 5.1, Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise Noted). Section 5 Updated/Changed ICDD and IDDD test conditions and footnote in Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted). Section 5.2 Deleted "Future variants..." footnote from table Section 6.7.1 Table 6-15, PLLC1 Clock Frequency Ranges: • Updated/Changed PLLOUT 1.2V-CVDD max value from "700 MHz" to "600 MHz" for -6/-5/-4/-L/-Q6/-Q5/-Q4 devices. • Updated/Changed SYSCLK1 1.05V-CVDD max value from "560 MHz" to "520 MHz" for -7 devices. Section 6.7.1 Updated/Changed sentence from "TI requires EMI filter manufacturer Murata..." to "TI recommends EMI filter manufacturer Murata..." Section 6.7.4 Deleted "(-4, -4Q, -4S, -5, -5Q, -5S, -6)" from Table 6-19 title, Timing Requirements for MXI/CLKIN. Revision History 6 Submit Documentation Feedback |
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