PHYSICAL CHARACTERISTICS

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19

38

37

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32

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27

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21

20

VR_ANA

AVDD

AVSS

AVSS

PLL_FLTM

PLL_FLTP

AVSS

MCLK

RESET

PDN

DVDD

DVSS

DVSS_OSC

OSC_RES

VR_OSC

MUTE

SDA

SCL

LRCLK

PWM_1

PWM_2

PWM_3

PWM_4

PWM_5

PWM_6

VALID2

VALID1

VR_DIG

DVSS

DVSS

BKND_ERR

SDIN1

SDIN2

SDIN3

SDIN4

SDOUT

RESERVED

SCLK

DBT PACKAGE

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P0034-01

TAS5086

Table 1. TERMINAL FUNCTIONS

TERMINAL

5-V

DESCRIPTION

TOLERANT

NAME

NO.

AVDD

2

P

3.3-V analog power supply

3, 4,

AVSS

P

Analog supply ground

7

Active-low. A back-end error sequence is generated by applying logic

BKND_ERR

27

DI

Pullup

LOW to this terminal. BKND_ERR results in no change to any system

parameters while VALID2 goes low.

DVDD

11

P

3.3-V digital power supply

12,

DVSS

28,

P

Digital ground

29

DVSS_OSC

13

P

Digital ground for oscillator

LRCLK

19

DI

5-V

Pulldown

Input serial audio data left/right clock (sampling rate clock)

MCLK is a 3.3-V clock master clock input. The input frequency of this

MCLK

8

DI

5-V

Pulldown

clock can range from 4 MHz to 50 MHz.

Performs a soft mute of outputs, active-low (muted signal = a logic low,

normal operation = a logic high). The mute control provides a noiseless

MUTE

16

DI

5-V

Pullup

volume ramp to silence. Releasing mute provides a noiseless ramp to

previous volume.

OSC_RES

14

AO

Oscillator trim resistor

(1)

TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2)

All pullups are 20-

µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure

proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive

inputs with pullups must be able to sink 20

µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be

able to source 20

µA while maintaining a logic-1 drive level.

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