tsu

thold

Dn

CLKIN

SN75LVDS83C

www.ti.com

SLLSE66A

– OCTOBER 2010 – REVISED SEPTEMBER 2011

SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 0, equal D1, D9,

-0.15

0

0.15

ns

D20, D5)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 1, equal D0, D8,

ns

D19, D27)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 2, equal D7, D18,

ns

D26. D23)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 3; equal D6, D15,

ns

|Input clock jitter|

D25, D17)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 4, equal D4, D14,

ns

D24, D16)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 5, equal D3, D13,

ns

D22, D11)

Delay time, CLKOUT

↑ after Yn valid

(serial bit position 6, equal D2, D12,

ns

D21, D10)

Output clock period

ns

±26

Figure 8

ps

±44

modulated at 3MHz, see Figure 8

High-level output clock pulse duration

ns

Differential output voltage transition

See Figure 4

200

250

800

ps

Enable time, SHTDN

↑ to phase lock

15

µs

(Yn valid)

Disable time, SHTDN

↓ to off-state

13

ns

(CLKOUT high-impedance)

(1)

(2)

|Input clock jitter| is the magnitude of the change in the input clock period.

(3)

The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed

over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.

PARAMETER MEASUREMENT INFORMATION

All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.

CLKSEL = 0V.

Figure 3. Set Up and Hold Time Definition

Copyright

© 2010–2011, Texas Instruments Incorporated

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