SN65LVDS1, SN65LVDS2, SN65LVDT2

SLLS373L – JULY 1999 – REVISED DECEMBER 2014

www.ti.com

7.6 Receiver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MAX

UNIT

Positive-going differential input voltage

100

threshold

See Figure 11

mV

Negative-going differential input voltage

–100

threshold

1.9

High-level output voltage

V

2.4

Low-level output voltage

0.25

0.4

V

Supply current

No load, Steady state

4

7

mA

–20

–2

LVDS2

–3

–1.2

Input current (A or B inputs)

μA

–40

-4

LVDT2

–6

–2.4

Differential input current

LVDS2

–2

2

μA

LVDS2

20

Power-off input current (A or B

μA

inputs)

LVDT2

40

Differential input resistance

LVDT2

90

111

132

Ω

Input capacitance

5.8

pF

Output capacitance

3.4

pF

(1)

The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet.

(2)

All typical values are at 25°C and with a 2.7-V supply.

7.7 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Propagation delay time, low-to-high-level output

1.5

3.1

ns

Propagation delay time, high-to-low-level output

1.8

3.1

ns

Differential output signal rise time

0.6

1

ns

See Figure 13

Differential output signal fall time

0.7

1

ns

(2)

0.3

ns

(1)

All typical values are at 25°C and with a 3.3-V supply.

(2)

6

Submit Documentation Feedback

Copyright © 1999–2014, Texas Instruments Incorporated

Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2