PC87351 datasheet(7/86 Pages) NSC

Part #	PC87351

Description	PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control

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Manufacturer	NSC [National Semiconductor (TI)]

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Table of Contents

Highlights....................................................................................................................................................... 1

Datasheet Revision Record .................................................................................................................... 4

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAM ......................................................................................................... 11

1.2

SIGNAL/PIN DIRECTORY ........................................................................................................ 12

1.3

PIN MULTIPLEXING ................................................................................................................. 16

1.4

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 17

1.4.1

Clock ............................................................................................................................ 17

1.4.2

Fan Speed Control ...................................................................................................... 17

1.4.3

FDC (Including PPM) ................................................................................................... 17

1.4.4

General-Purpose Input/Output (GPIO) Ports ............................................................... 19

1.4.5

Host Interface .............................................................................................................. 20

1.4.6

Infrared (IR) ................................................................................................................. 20

1.4.7

Keyboard and Mouse Controller (KBC) ....................................................................... 21

1.4.8

Parallel Port ................................................................................................................. 22

1.4.9

Power and Ground ...................................................................................................... 22

1.4.10

Serial Ports 1 and 2 ..................................................................................................... 23

1.4.11

Strapping ..................................................................................................................... 23

1.4.12

System Wake-Up Control ............................................................................................ 23

2.0

Device Architecture and Configuration

2.1

OVERVIEW ............................................................................................................................... 24

2.2

CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 25

2.2.1

The Index-Data Register Pair ...................................................................................... 25

2.2.2

Banked Logical Device Registers ................................................................................ 25

2.2.3

Standard PnP Register Definitions .............................................................................. 26

2.2.4

Overview of PnP Standard Registers .......................................................................... 28

2.2.5

Default Configuration Setup ........................................................................................ 29

2.2.6

Address Decoding ....................................................................................................... 29

2.2.7

The Internal Clocks ...................................................................................................... 29

2.3

REGISTER TYPE ABBREVIATIONS ........................................................................................ 30

2.4

SUPERI/O CONFIGURATION AND CONTROL REGISTERS ................................................. 30

2.4.1

SuperI/O Register Map ................................................................................................ 30

2.4.2

SuperI/O ID Register (SID) .......................................................................................... 30

2.4.3

SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 31

2.4.4

SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 32

2.4.5

SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 33

2.4.6

SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 34

2.4.7

SuperI/O Revision ID Register (SRID) ........................................................................ 34

2.5

PARALLEL PORT MULTIPLEXER (PPM) ................................................................................ 35

2.5.1

PPM Mode ...................................................................................................................35

2.5.2

TRI-STATE Control of Parallel Port Pins ..................................................................... 36

2.6

FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 ................................................... 37

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