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PC87317 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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PC87317 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 272 page  3 Highlights www.national.com — A Fail-safe event occurs (power-save mode detected but the system is hung up) — Software turns power off — Any one of 10 programmable Power Management trigger events occur q Two Serial Ports (UART1 and 2) that provide: — Fully compatible with the 16550A and the 16450 — Extended UART mode — 13 IRQ channel options — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud q An enhanced UART with IR interface on the UART2 that supports: — IrDA 1.0-SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control circuitry — DMA handshake signal routing for either 1 or 2 chan- nels — A PnP compatible external transceiver q A bidirectional parallel port that includes: — A modifiable address that is referenced by a 16-bit programmable register — Software or hardware control — 13 IRQ channel options — Four 8-bit DMA channel options — Demand mode DMA support — An Enhanced Parallel Port (EPP) that is compatible with the new version EPP 1.9, and is IEEE 1284 compliant — An Enhanced Parallel Port (EPP) that also supports version EPP 1.7 of the Xircom specification — Support for an Enhanced Parallel Port (EPP) as mode 4 of the Extended Capabilities Port (ECP) — An Extended Capabilities Port (ECP) that is IEEE 1284 compliant, including level 2 — Selection of internal pull-up or pull-down resistor for Paper End (PE) pin — Reduction of PCI bus utilization by supporting a de- mand DMA mode mechanism and a DMA fairness mechanism — A protection circuit that prevents damage to the par- allel port when a printer connected to it powers up or is operated at high voltages — Output buffers that can sink and source14 mA q Three general-purpose pins for three separate program- mable chip select signals, as follows: — Can be programmed for game port control — The Chip Select 0 (CS0) signal produces open drain output and is powered by the VCCH — The Chip Select 1 (CS1) and 2 (CS2) signals have push-pull buffers and are powered by the main VDD — Decoding of chip select signals depends on the ad- dress and the Address Enable (AEN) signals, and can be qualified using the Read (RD) and Write (WR) signals. q 24 single-bit GPIO ports: — Modifiable addresses that are referenced by a 16-bit programmable register — Programmable direction for each signal (input or out- put) — Programmable drive type for each output pin (open- drain or push-pull) — Programmable option for internal pull-up resistor on each input pin — Configuration-Lock options — Several signals may be selected as interrupt triggers — A back-drive protection circuit q An X-bus data buffer that connects the 8-bit X data bus to the ISA data bus q Clock source options: — Source is a 32.768 KHz crystal - an internal frequen- cy multiplier generates all the required internal fre- quencies. — Source may be either a 48 MHz or 24 MHz clock in- put signal. q Enhanced Power Management (PM), including: — Special configuration registers for power down — WATCHDOG timer for power-saving strategies — Reduced current leakage from pins — Low-power CMOS technology — Ability to shut off clocks to all modules — LED control powered by VCCH q General features include: — All accesses to the SuperI/O chip activate a Zero Wait State (ZWS) signal, except for accesses to the Enhanced Parallel Port (EPP) and to configuration registers — Access to all configuration registers is through an In- dex and a Data register, which can be relocated within the ISA I/O address space — 160-pin Plastic Quad Flatpack (PQFP) package |
Similar Part No. - PC87317 |
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Similar Description - PC87317 |
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