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VSC8164QR Datasheet(PDF) 5 Page - Vitesse Semiconductor Corporation |
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VSC8164QR Datasheet(HTML) 5 Page - Vitesse Semiconductor Corporation |
5 / 16 page VITESSE SEMICONDUCTOR CORPORATION reliminary Datasheet SC8164 2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux G52239-0, Rev. 3.3 VITESSE SEMICONDUCTOR CORPORATION Page 5 5/17/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Figure 7: Differential and Single Ended Input and Output Voltage Measurement Table 1: AC Characteristics Parameters Description Min Max Units Conditions tpdd Data valid from falling edge of CLK16O+ 0800 ps. tpd32 CLK32O transition from falling edge of CLK16O+ 01.0 ns. tDR, tDF D[15:0]+/- rise and fall times — 400 ps 20% to 80% into 50 Ohm load. See Figure 7 tCLKR, tCLKF CLK16O+/- rise and fall times — 250 ps 20% to 80% into 50 Ohm load. See Figure 7 CLK16OD CLK16O+/- duty cycle distortion 45 55 % of clock cycle High speed clock input at 2.488GHz tdsu DI+ setup time with respect to falling edge of HSCLKI+ 100 — ps tdh DI+ hold time with respect to falling edge of HSCLKI+ 75 — ps HSCLKID HSCLKI+/- duty cycle distortion 40 60 % of clock cycle Single Ended Swing Differential Swing = α = α a a b b * Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single ended swing. Differential swing is specified as equal in magnitude to single ended swing. |
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