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LMK61E2-156M25SIAT Datasheet(PDF) 6 Page - Texas Instruments |
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LMK61E2-156M25SIAT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 22 page  6 LMK61E0-050M, LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M SNAS676B – OCTOBER 2015 – REVISED MARCH 2017 www.ti.com Product Folder Links: LMK61E0-050M LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2- 100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61I2-100M Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing. (3) Ensured by design. (4) Ensured by characterization. 6.8 HCSL Output Characteristics (1) VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT Output frequency 10 400 MHz VOH Output high voltage 600 850 mV VOL Output low voltage –100 100 mV VCROSS Absolute crossing voltage(2)(3) 250 475 mV VCROSS-DELTA Variation of VCROSS (2) (3) 0 140 mV dV/dt Slew rate(4) 0.8 2 V/ns PN-Floor Output phase noise floor (fOFFSET > 10 MHz) 100 MHz –164 dBc/Hz ODC Output duty cycle(4) 45% 55% 6.9 OE Input Characteristics VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input high voltage 1.4 V VIL Input low voltage 0.6 V IIH Input high current VIH = VDD –40 40 uA IIL Input low current VIL = GND –40 40 uA CIN Input capacitance 2 pF (1) Ensured by characterization. 6.10 Frequency Tolerance Characteristics (1) VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fT Total frequency tolerance LMK61X2: All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) –50 50 ppm LMK61X0: All output formats, frequency bands and device junction temperature up to 115°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (5 years at 40°C) –25 25 ppm (1) Ensured by characterization. (2) Ensured by design. 6.11 Power-On/Reset Characteristics (VDD) VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VTHRESH Threshold voltage(1) 2.72 2.95 V VDROOP Allowable voltage droop(2) 0.1 V tSTARTUP Start-up time (1) Time elapsed from VDD at 3.135 V to output enabled 10 ms tOE-EN Output enable time(2) Time elapsed from OE at VIH to output enabled 50 us tOE-DIS Output disable time(2) Time elapsed from OE at VIL to output disabled 50 us |
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