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PCI2050BPDVG4 Datasheet(PDF) 2 Page - Texas Instruments

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Part # PCI2050BPDVG4
Description  PCI-to-PCI Bridge
Download  88 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PCI2050BPDVG4 Datasheet(HTML) 2 Page - Texas Instruments

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Contents
Section
Title
Page
1 Introduction
1−1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features
1−1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Related Documents
1−2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Trademarks
1−2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Ordering Information
1−2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions
2−1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions
3−1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Introduction to the PCI2050B Bridge
3−1
. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Write Combining
3−2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
66-MHz Operation
3−2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
PCI Commands
3−2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Configuration Cycles
3−3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Special Cycle Generation
3−5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Secondary Clocks
3−5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Bus Arbitration
3−6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Primary Bus Arbitration
3−6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
Internal Secondary Bus Arbitration
3−6
. . . . . . . . . . . . . . . . . . . .
3.6.3
External Secondary Bus Arbitration
3−7
. . . . . . . . . . . . . . . . . . .
3.7
Decode Options
3−7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
System Error Handling
3−7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Posted Write Parity Error
3−7
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
Posted Write Time-Out
3−7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3
Target Abort on Posted Writes
3−7
. . . . . . . . . . . . . . . . . . . . . . . .
3.8.4
Master Abort on Posted Writes
3−8
. . . . . . . . . . . . . . . . . . . . . . .
3.8.5
Master Delayed Write Time-Out
3−8
. . . . . . . . . . . . . . . . . . . . . .
3.8.6
Master Delayed Read Time-Out
3−8
. . . . . . . . . . . . . . . . . . . . . .
3.8.7
Secondary SERR
3−8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
Parity Handling and Parity Error Reporting
3−8
. . . . . . . . . . . . . . . . . . . . . .
3.9.1
Address Parity Error
3−8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2
Data Parity Error
3−8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10
Master and Target Abort Handling
3−8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11
Discard Timer
3−9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12
Delayed Transactions
3−9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13
Mode Selection
3−9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14
CompactPCI Hot-Swap Support
3−10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15
JTAG Support
3−11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1
Test Port Instructions
3−11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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