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PCI2050BIGHK Datasheet(PDF) 6 Page - Texas Instruments |
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PCI2050BIGHK Datasheet(HTML) 6 Page - Texas Instruments |
6 / 88 page vii List of Tables Table Title Page 2−1 208-Terminal PDV Signal Names Sorted by Terminal Number 2−4 . . . . . . . . 2−2 208-Terminal PPM Signal Names Sorted by Terminal Number 2−5 . . . . . . . . 2−3 257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number 2−6 . . . 2−4 208-Terminal PDV Signal Names Sorted Alphabetically 2−8 . . . . . . . . . . . . . . 2−5 208-Terminal PPM Signal Names Sorted Alphabetically 2−9 . . . . . . . . . . . . . . 2−6 257-Terminal GHK/ZHK Signal Names Sorted Alphabetically 2−10 . . . . . . . . . 2−7 Primary PCI System Terminals 2−12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−8 Primary PCI Address and Data Terminals 2−12 . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9 Primary PCI Interface Control Terminals 2−13 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−10 Secondary PCI System Terminals 2−14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11 Secondary PCI Address and Data Terminals 2−15 . . . . . . . . . . . . . . . . . . . . . . . 2−12 Secondary PCI Interface Control Terminals 2−16 . . . . . . . . . . . . . . . . . . . . . . . . . 2−13 JTAG Interface Terminals 2−16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−14 Miscellaneous Terminals 2−17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15 Power Supply Terminals 2−17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 PCI Command Definitions 3−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 PCI S_AD31−S_AD16 During the Address Phase of a Type 0 Configuration Cycle 3−5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 Configuration via MS0 and MS1 3−10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 JTAG Instructions and Op Codes 3−11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 Boundary Scan Terminal Order 3−11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 Clock Mask Data Format 3−15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 Bridge Configuration Header 4−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 Command Register Description 4−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3 Status Register Description 4−4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4 Secondary Status Register Description 4−10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 Bridge Control Register Description 4−15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1 Chip Control Register Description 5−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2 Extended Diagnostic Register Description 5−2 . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3 Arbiter Control Register Description 5−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−4 P_SERR Event Disable Register Description 5−4 . . . . . . . . . . . . . . . . . . . . . . . 5−5 GPIO Output Data Register Description 5−5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6 GPIO Output Enable Register Description 5−5 . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7 GPIO Input Data Register Description 5−6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−8 Secondary Clock Control Register Description 5−7 . . . . . . . . . . . . . . . . . . . . . . 5−9 P_SERR Status Register Description 5−8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−10 Power-Management Capabilities Register Description 5−9 . . . . . . . . . . . . . . . 5−11 Power-Management Control/Status Register 5−10 . . . . . . . . . . . . . . . . . . . . . . . |
Similar Part No. - PCI2050BIGHK |
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Similar Description - PCI2050BIGHK |
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