From Output

Under Test

Tester Channel

C = 50 pF

C = 5 pF for Disable Time

L

L

DLP3000

DLPS022B – JANUARY 2012 – REVISED MARCH 2015

www.ti.com

6.7 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

Setup time: DATA before rising or falling edge of DCLK

1

Setup time: TRC before rising or falling edge of DCLK

1

ns

Setup time: SCTRL before rising or falling edge of DCLK

1

Setup time: LOADB low before rising edge of DCLK

1

ns

Setup time: SAC_BUS low before rising edge of SAC_CLK

1

ns

Setup time: DRC_BUS high before rising edge of SAC_CLK

1

ns

Setup time: DRC_STROBE high before rising edge of SAC_CLK

1

ns

Hold time: DATA after rising or falling edge of DCLK

1

Hold time: TRC after rising or falling edge of DCLK

1

ns

Hold time: SCTRL after rising or falling edge of DCLK

1

Hold time: LOADB low after falling edge of DCLK

1

ns

Hold time: SAC_BUS low after rising edge of SAC_CLK

1

ns

Hold time: DRC_BUS after rising edge of SAC_CLK

1

ns

Hold time: DRC_STROBE after rising edge of SAC_CLK

1

ns

Clock cycle: DCLK

12.5

16.67

ns

Clock cycle: SAC_CLK

12.5

16.67

ns

Pulse duration high or low: DCLK

5

ns

Pulse duration low: LOADB

7

ns

Pulse duration high or low: SAC_CLK

5

ns

Pulse duration high: DRC_STROBE

7

ns

Rise time: DCLK / SAC_CLK

2.5

ns

Rise time: DATA / TRC / SCTRL / LOADB

2.5

Fall time: DCLK / SAC_CLK

2.5

ns

Fall time: DATA / TRC / SCTRL / LOADB

2.5

6.8 Measurement Conditions

The data sheet provides timing at the device pin. For output timing analysis, consider the tester pin electronics

and its transmission line effects. Figure 2 shows an equivalent test load circuit for the output under test. The load

capacitance value stated is only for characterization and measurement of AC timing signals. This load

capacitance value does not indicate the maximum load the device is capable of driving.

Figure 2. Test Load Circuit for AC Timing Measurements

10

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