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CDCVF857RHA Datasheet(PDF) 1 Page - Texas Instruments |
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CDCVF857RHA Datasheet(HTML) 1 Page - Texas Instruments |
1 / 23 page www.ti.com FEATURES DESCRIPTION APPLICATIONS CDCVF857 SCAS047F – MARCH 2003 – REVISED MAY 2007 2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER • Spread-Spectrum Clock Compatible The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a • Operating Frequency: 60 MHz to 220 MHz differential clock input pair (CLK, CLK) to 10 • Low Jitter (Cycle-Cycle): ±35 ps differential pairs of clock outputs (Y[0:9], Y[0:9]) and • Low Static Phase Offset: ±50 ps one differential pair of feedback clock outputs • Low Jitter (Period): ±30 ps (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks • 1-to-10 Differential Clock Distribution (SSTL2) (FBIN, FBIN), and the analog power input (AVDD). • Best in Class for V OX = VDD/2 ±0.1 V When PWRDWN is high, the outputs switch in phase • Operates From Dual 2.6-V or 2.5-V Supplies and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state • Available in a 40-Pin MLF Package, 48-Pin (3-state) and the PLL is shut down (low-power TSSOP Package, 56-Ball MicroStar Junior™ mode). The device also enters this low-power mode BGA Package when the input frequency falls below a suggested • Consumes < 100-µA Quiescent Current detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects • External Feedback Pins (FBIN, FBIN) Are Used the low frequency condition and, after applying a to Synchronize the Outputs to the Input >20-MHz input signal, this detection circuit turns the Clocks PLL on and enables the outputs. • Meets/Exceeds JEDEC Standard (JESD82-1) When AVDD is strapped low, the PLL is turned off For DDRI-200/266/333 Specification and bypassed for test purposes. The CDCVF857 is • Meets/Exceeds Proposed DDRI-400 also able to track spread spectrum clocking for Specification (JESD82-1A) reduced EMI. • Enters Low-Power Mode When No CLK Input Because the CDCVF857 is based on PLL circuitry, it Signal Is Applied or PWRDWN Is Low requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both • DDR Memory Modules (DDR400/333/266/200) commercial and industrial temperature ranges. • Zero-Delay Fan-Out Buffer A A AVAILABLE OPTIONS TA TSSOP (DGG) 40-Pin MLF 56-Ball BGA(1) –40 °C to 85°C CDCVF857DGG CDCVF857RTB CDCVF857GQL –40 °C to 85°C CDCVF857RHA CDCVF857ZQL (1) Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum TA allowed is 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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