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CDCE937PWRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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CDCE937PWRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 39 page 2 CDCE937, CDCEL937 SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCE937 CDCEL937 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Pin Configuration and Functions ......................... 4 6 Specifications......................................................... 5 6.1 Absolute Maximum Ratings ...................................... 5 6.2 ESD Ratings.............................................................. 5 6.3 Recommended Operating Conditions ....................... 5 6.4 Thermal Information .................................................. 6 6.5 Electrical Characteristics........................................... 6 6.6 Timing Requirements: CLK_IN ................................. 8 6.7 Timing Requirements: SDA/SCL .............................. 8 6.8 EEPROM Specification ............................................. 8 6.9 Typical Characteristics .............................................. 9 7 Parameter Measurement Information ................ 10 8 Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 15 8.5 Programming........................................................... 16 8.6 Register Maps ......................................................... 17 9 Application and Implementation ........................ 24 9.1 Application Information............................................ 24 9.2 Typical Application .................................................. 24 10 Power Supply Recommendations ..................... 29 11 Layout................................................................... 29 11.1 Layout Guidelines ................................................. 29 11.2 Layout Example .................................................... 30 12 Device and Documentation Support ................. 31 12.1 Device Support...................................................... 31 12.2 Documentation Support ........................................ 31 12.3 Receiving Notification of Documentation Updates 31 12.4 Community Resources.......................................... 31 12.5 Trademarks ........................................................... 31 12.6 Electrostatic Discharge Caution ............................ 31 12.7 Glossary ................................................................ 31 13 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2010) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Changed Applications............................................................................................................................................................. 1 • Changed Thermal Resistance Junction to Ambient, RθJA, values in Thermal Information From: 89 (0 lfm), 75 (150 lfm), 74 (200 lfm), 74 (250 lfm), and 69 (500 lfm) To: 89.04 .................................................................................................. 6 • Deleted Input Capacitance figure ......................................................................................................................................... 19 Changes from Revision E (October 2009) to Revision F Page • Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, and PLL3 Configure Register Table ...................................................................................................................................................................... 20 • Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4 ................... 26 • Changed under Example, fifth row, N", 2 places TO N' ....................................................................................................... 26 Changes from Revision D (September 2009) to Revision E Page • Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more information. ...................................................................................................... 14 Changes from Revision C (January 2009) to Revision D Page • Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table ................... 5 |
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