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PC16552DV Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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PC16552DV Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 21 page 30 AC Electrical Characteristics TA e 0 Cto a70 C VDD ea5V g10% (Continued) Symbol Parameter Conditions Min Max Units TRANSMITTER tHR Delay from WR (WR THR) 40 ns to Reset Interrupt tIR Delay from RD (RD IIR) to Reset 40 ns Interrupt (THRE) tIRS Delay from Initial INTR Reset 824 BAUDOUT to Transmit Start Cycles tSI Delay from Initial Write to Interrupt (Note 1) 16 24 BAUDOUT Cycles tSTI Delay from Start to Interrupt (THRE) (Note 1) 8 BAUDOUT Cycles tSXA Delay from Start to TXRDY Active 8 BAUDOUT Cycles tWXI Delay from Write to TXRDY Inactive 25 ns MODEM CONTROL tMDO Delay from WR (WR MCR) 40 ns to Output tRIM Delay to Reset Interrupt from 78 ns RD (RD MSR) tSIM Delay to Set Interrupt from MODEM Input 40 ns Note 1 This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode Operation) 40 Timing Waveforms All timings are referenced to valid 0 and valid 1 External Clock Input (24 MHz Max) TLC9426 – 2 AC Test Points TLC9426 – 3 Note 2 The 24V and 04V levels are the voltages that the inputs are driven to during AC testing Note 3 The 20V and 08V levels are the voltages at which the timing tests are made BAUDOUT Timing TLC9426 – 4 5 |
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