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NSC800V Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # NSC800V
Description  NSC800TM High-Performance Low-Power CMOS Microprocessor
Download  76 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

NSC800V Datasheet(HTML) 4 Page - National Semiconductor (TI)

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40 AC Electrical Characteristics VCC e 5V g10% GND e 0V unless otherwise specified
Symbol
Parameter
NSC800-1
NSC800-3
NSC800-35
NSC800-4
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
tX
Period at XIN and XOUT
500
3333 200 3333
142
3333
125 3333
ns
Pins
T
Period at Clock Output
1000 6667 400 6667
284
6667
250 6667
ns
(e2tX)
tR
Clock Rise Time
110
110
90
80
ns
Measured from
10% – 90% of signal
tF
Clock Fall Time
70
60
55
50
ns
Measured from
10% – 90% of signal
tL
Clock Low Time
435
150
90
80
ns
50% duty cycle square
wave input on XIN
tH
Clock High Time
450
145
85
75
ns
50% duty cycle square
wave input on XIN
tACC(OP)
ALE to Valid Data
1340
490
340
300
ns
Add t for each WAIT STATE
tACC(MR)
ALE to Valid Data
1875
620
405
360
ns
Add t for each WAIT STATE
tAFR
AD(0 – 7) Float after
0
0
0
0
ns
RD Falling
tBABE
BACK Rising to Bus
1000
400
300
250
ns
Enable
tBABF
BACK Falling to
50
50
50
50
ns
Bus Float
tBACL
BACK Fall to CLK
425
125
60
55
ns
Falling
tBRH
BREQ Hold Time
0
0
0
0
ns
tBRS
BREQ Set-Up Time
100
50
50
45
ns
tCAF
Clock Falling ALE
0
70
0
65
0
60
0
55
ns
Falling
tCAR
Clock Rising to ALE
0
100
0
100
0
90
0
80
ns
Rising
tCRD
Clock Rising to
100
90
90
80
ns
Read Rising
tCRF
Clock Rising to
80
70
70
65
ns
Refresh Falling
tDAI
ALE Falling to INTA
445
160
95
85
ns
Falling
tDAR
ALE Falling to
400
575
160
250
100
180
90
160
ns
RD Falling
tDAW
ALE Falling to
900
1010 350
420
225
300
200
265
ns
WR Falling
tD(BACK)1 ALE Falling to BACK
2460
975
635
560
ns
Add t for each WAIT state
Falling
Add t for opcode fetch cycles
tD(BACK)2 BREQ Rising to BACK
500
1610 200
700
140
540
125
475
ns
Rising
tD(I)
ALE Falling to INTR
1360
475
284
250
ns
Add t for each WAIT state
NMI RSTA-C PS
Add t for opcode fetch cycles
BREQ Inputs Valid
tDPA
Rising PS to
500
1685 200
760
140
580
125
510
ns
See
Figure 14 also
Falling ALE
tD(WAIT)
ALE Falling to
550
250
170
125
ns
WAIT Input Valid
OP
Opcode Fetch
MR
Memory Read
4


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