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PC16550D Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. PC16550D
Description  PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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 4 page
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30
AC Electrical Characteristics TA e 0 Cto a70 C VDD ea5V g10%
Symbol
Parameter
Conditions
Min
Max
Units
tADS
Address Strobe Width
60
ns
tAH
Address Hold Time
0
ns
tAR
RD RD Delay from Address
(Note 1)
30
ns
tAS
Address Setup Time
60
ns
tAW
WR WR Delay from Address
(Note 1)
30
ns
tCH
Chip Select Hold Time
0
ns
tCS
Chip Select Setup Time
60
ns
tCSR
RD RD Delay from Chip Select
(Note 1)
30
ns
tCSW
WR WR Delay from Select
(Note 1)
30
ns
tDH
Data Hold Time
30
ns
tDS
Data Setup Time
30
ns
tHZ
RD RD to Floating Data Delay
100 pF loading (Note 3)
0
100
ns
tMR
Master Reset Pulse Width
5000
ns
tRA
Address Hold Time from RD RD
(Note 1)
20
ns
tRC
Read Cycle Delay
125
ns
tRCS
Chip Select Hold Time from RD RD
(Note 1)
20
ns
tRD
RD RD Strobe Width
125
ns
tRDD
RD RD to Driver EnableDisable
100 pF loading (Note 3)
60
ns
tRVD
Delay from RD RD to Data
100 pF loading
60
ns
tWA
Address Hold Time from WR WR
(Note 1)
20
ns
tWC
Write Cycle Delay
150
ns
tWCS
Chip Select Hold Time from WR WR
(Note 1)
20
ns
tWR
WR WR Strobe Width
100
ns
tXH
Duration of Clock High Pulse
External Clock (8 Max)
55
ns
tXL
Duration of Clock Low Pulse
External Clock (8 Max)
55
ns
RC
Read Cycle e tAR a tRD a tRC
280
ns
WC
Write Cycle e tAW a tWR a tWC
280
ns
Baud Generator
N
Baud Divisor
1
216b1
tBHD
Baud Output Positive Edge Delay
100 pF Load
175
ns
tBLD
Baud Output Negative Edge Delay
100 pF Load
175
ns
tHW
Baud Output Up Time
fX e 8 d2 100 pF Load
75
ns
tLW
Baud Output Down Time
fX e 8 d2 100 pF Load
100
ns
Receiver
tRAI
Delay from Active Edge
ns
of RD to Reset Interrupt
tRINT
Delay from RD RD
100 pF Load
(RD RBRor RD LSR)
1000
ns
to Reset Interrupt
tRXI
Delay from RD RBR
290
ns
to RXRDY Inactive
tSCD
Delay from RCLK to Sample Time
2000
ns
tSINT
Delay from Stop to Set Interrupt
(Note 2)
1
RCLK
Cycles
Note 1
Applicable only when ADS is tied low
Note 2
In the FIFO mode (FCR0e1) the trigger level interrupts the receiver data available indication the active RXRDY indication and the overrun error indication
will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes these
indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs
Note 3
Charge and discharge time is determined by VOL VOH and the external loading
Note 4
These specifications are preliminary
4




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