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ADC12D1620CCMPR Datasheet(PDF) 11 Page - Texas Instruments |
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ADC12D1620CCMPR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 82 page VDR DR GND + - + - VDR DR GND + - + - 11 ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Product Folder Links: ADC12D1620QML-SP Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions: Analog Front-End and Clock Pins (continued) PIN TYPE DESCRIPTION EQUIVALENT CIRCUIT NAME NO. DId11+, DId11– DId10+, DId10– DId9+, DId9– DId8+, DId8– DId7+, DId7– DId6+, DId6– DId5+, DId5– DId4+, DId4– DId3+, DId3– DId2+, DId2– DId1+,DId1 – DId0+, DId0– · DQd11+, DQd11– DQd10+, DQd10– DQd9+, DQd9– DQd8+, DQd8– DQd7+, DQd7– DQd6+, DQd6– DQd5+, DQd5– DQd4+, DQd4– DQd3+, DQd3– DQd2+, DQd2– DQd1+, DQd1– DQd0+, DQd0– A18/A19 B17/C16 A16/B16 B15/C15 C14/D14 A14/B14 B13/C13 C12/D12 A12/B12 B11/C11 C10/D10 A10/B10 · Y18/Y19 W17/V16 Y16/W16 W15/V15 V14/U14 Y14/W14 W13/V13 V12/U12 Y12/W12 W11/V11 V10/U10 Y10/W10 O Delayed I- and Q-channel digital data outputs. In non-demux mode, these outputs are tri-state. In demux mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the non- delayed data; that is, the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. ORI+, ORI– ORQ+, ORQ– K17/K18 L17/L18 O Out-of-range output for the I and Q channel. This differential output is asserted logic-high while the over- or under-range condition exists; that is, the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current data, with which it is clocked out. If used, terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. |
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