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66AK2H14 Datasheet(PDF) 11 Page - Texas Instruments |
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66AK2H14 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 355 page  66AK2H14/12/06 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SPRS866E—November 2012—Revised November 2013 Figure 10-10 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Figure 10-11 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Figure 10-12 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . 296 Figure 10-13 Reset Type Status Register (RSTYPE). . . . . . . . 296 Figure 10-14 Reset Control Register (RSTCTRL) . . . . . . . . . . 297 Figure 10-15 Reset Configuration Register (RSTCFG) . . . . . 297 Figure 10-16 Reset Isolation Register (RSISO) . . . . . . . . . . . . 298 Figure 10-17 Main PLL Control Register 0 (MAINPLLCTL0) 299 Figure 10-18 Main PLL Control Register 1 (MAINPLLCTL1) 299 Figure 10-19 ARM PLL Control Register 0 (ARMPLLCTL0) . 300 Figure 10-20 ARM PLL Control Register 1 (ARMPLLCTL1) . 301 Figure 10-21 Main PLL Controller/SRIO/HyperLink/PCIe/USB Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 303 Figure 10-22 Main PLL Transition Time . . . . . . . . . . . . . . . . . . 304 Figure 10-23 HYP0CLK, HYP1CLK, and PCIECLK Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Figure 10-24 USBCLK Rise and Fall Times . . . . . . . . . . . . . . . . 304 Figure 10-25 DDR3A PLL and DDR3B PLL Block Diagram . 305 Figure 10-26 DDR3A PLL and DDR3B PLL Control Register 0 (DDR3APLLCTL0/DDR3BPLLCTL0) . . . . . . . . . . 305 Figure 10-27 DDR3A PLL and DDR3B PLL Control Register 1 (DDR3APLLCTL0/DDR3BPLLCTL1) . . . . . . . . . . 306 Figure 10-28 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . 307 Figure 10-29 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . 307 Figure 10-30 PASS PLL Control Register 0 (PASSPLLCTL0) 308 Figure 10-31 PASS PLL Control Register 1 (PASSPLLCTL1) 308 Figure 10-32 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Figure 10-33 NMI and LRESET Timing . . . . . . . . . . . . . . . . . . . 310 Figure 10-34 I2C Module Block Diagram . . . . . . . . . . . . . . . . . 313 Figure 10-35 I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . 315 Figure 10-36 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . 316 Figure 10-37 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode. . . . . . . . . . . . . . . . . . . . .318 Figure 10-38 SPI Additional Timings for 4-Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . .318 Figure 10-39 HyperLink Station Management Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 Figure 10-40 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 Figure 10-41 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 Figure 10-42 UART Receive Timing Waveform . . . . . . . . . . . .321 Figure 10-43 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . .321 Figure 10-44 UART Transmit Timing Waveform. . . . . . . . . . .322 Figure 10-45 UART RTS (Request-to-Send Output) – Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . .322 Figure 10-46 MACID1 Register (MMR Address 0x02620110) . . . . . . . . . . . . . . . .323 Figure 10-47 MACID2 Register (MMR Address 0x02620114) . . . . . . . . . . . . . . . .323 Figure 10-48 RFTCLK Select Register (CPTS_RFTCLK_SEL) 324 Figure 10-49 MDIO Input Timing. . . . . . . . . . . . . . . . . . . . . . . . .325 Figure 10-50 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . .325 Figure 10-51 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 Figure 10-52 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 Figure 10-53 EMIF16 Asynchronous Memory Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 Figure 10-54 EMIF16 Asynchronous Memory Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 Figure 10-55 EMIF16 EM_WAIT Read Timing Diagram . . . .332 Figure 10-56 EMIF16 EM_WAIT Write Timing Diagram . . . .332 Figure 10-57 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 Figure 10-58 JTAG Test-Port Timing. . . . . . . . . . . . . . . . . . . . . .344 |
Similar Part No. - 66AK2H14_17 |
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Similar Description - 66AK2H14_17 |
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