M24C64-DW6T datasheet(8/26 Pages) STMICROELECTRONICS

Part #	M24C64-DW6T

Description	64Kbit and 32Kbit Serial I짼C Bus EEPROM

Download	26 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

Logo

8 / 26 page

M24C64, M24C32

8/26

DEVICE OPERATION

The device supports the I2C protocol. This is sum-

marized in Figure 5.. Any device that sends data

on to the bus is defined to be a transmitter, and

any device that reads the data to be a receiver.

The device that controls the data transfer is known

as the bus master, and the other as the slave de-

vice. A data transfer can only be initiated by the

bus master, which will also provide the serial clock

for synchronization. The M24Cxx device is always

a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminates communica-

tion between the device and the bus master. A

Read command that is followed by NoAck can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a Write command triggers the internal Write

cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-

ful byte transfer. The bus transmitter, whether it be

bus master or slave device, releases Serial Data

(SDA) after sending eight bits of data. During the

9th clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change

only when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus master must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 3.

(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address”

(E2, E1, E0). To address the memory array, the 4-

bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on

a single I2C bus. Each one is given a unique 3-bit

code on the Chip Enable (E0, E1, E2) inputs.

When the Device Select Code is received, the de-

vice only responds if the Chip Enable Address is

the same as the value on the Chip Enable (E0, E1,

E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SDA) during the 9th bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 6. Operating Modes

Note: 1. X =

VIH or VIL.

Mode

RW bit

WC 1

Bytes

Initial Sequence

Current Address Read

1

X

1

START, Device Select, RW = 1

Random Address Read

0X

1

START, Device Select, RW = 0, Address

1

X

reSTART, Device Select, RW = 1

Sequential Read

1

X

≥ 1

Similar to Current or Random Address Read

Byte Write

0

VIL

1

START, Device Select, RW = 0

Page Write

0

VIL

≤ 32

START, Device Select, RW = 0

Similar Part No. - M24C64-DW6T

Manufacturer	Part #	Datasheet	Description
STMicroelectronics	M24C64-DF	465Kb / 42P	64-Kbit serial I2C bus EEPROM
	M24C64-DF	838Kb / 45P	64-Kbit serial I짼C bus EEPROM
	M24C64-DRDW3TG	608Kb / 40P	Automotive 64-Kbit serial IC bus EEPROM with 1 MHz clock
	M24C64-DRDW3TP	608Kb / 40P	Automotive 64-Kbit serial IC bus EEPROM with 1 MHz clock
	M24C64-DRDW8TG	1Mb / 41P	64-Kbit serial IC bus EEPROM - 105C operation

More results

Similar Description - M24C64-DW6T

Manufacturer	Part #	Datasheet	Description
Shenzhen Huazhimei Semi...	HM24C32	813Kb / 16P	32Kbit and 64Kbit Serial IC bus EEPROM
STMicroelectronics	M95640	590Kb / 39P	64Kbit and 32Kbit Serial SPI Bus EEPROM With High Speed Clock November 2003
Sanyo Semicon Device	LE25LA322	255Kb / 14P	Serial SPI EEPROM (SPI Bus) (32Kbit)
Sanyo Semicon Device	LE25LB642CT	372Kb / 14P	Serial SPI EEPROM (SPI Bus)(64Kbit)
STMicroelectronics	M95640-S	768Kb / 42P	32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock
Sanyo Semicon Device	LE25LB643	255Kb / 14P	Serial SPI EEPROM (SPI Bus) (64Kbit)
Asahi Kasei Microsystem...	AK6514C	131Kb / 18P	SPI bus 64Kbit Serial CMOS EEPROM
Sanyo Semicon Device	LE25CA322	223Kb / 14P	Serial SPI EEPROM (SPI Bus) (32Kbit)
Asahi Kasei Microsystem...	AK6512CA	130Kb / 17P	SPI bus 64Kbit Serial CMOS EEPROM
Asahi Kasei Microsystem...	AK6510C	135Kb / 18P	SPI bus 64Kbit Serial CMOS EEPROM

More results

M24C64-DW6T Datasheet(PDF) 8 Page - STMicroelectronics

M24C64-DW6T Datasheet(HTML) 8 Page - STMicroelectronics

Similar Part No. - M24C64-DW6T

Similar Description - M24C64-DW6T

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL