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AFE5808A Datasheet(PDF) 7 Page - Texas Instruments |
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AFE5808A Datasheet(HTML) 7 Page - Texas Instruments |
7 / 83 page AFE5808A www.ti.com SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015 Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. J6, J7, K8, AVDD_ADC L3, Supply 1.8-V Analog power supply for ADC M1, M2 C1, D1~D7, E3~E7, F3~F7, AVSS — Analog ground G1~G7, H3~H7,J3~J 5, K6 Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or through CLKM_ADC L2 I a 0.1-µF capacitor. Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal directly or CLKP_ADC L1 I through a 0.1-µF capacitor. Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the 4X and CLKM_16X F9 I 8X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode, this pin becomes the in-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used. Positive input of differential CW 16X clock. In 4X and 8X clock modes, this pin becomes the 4X or 8X CLKP CLKP_16X F8 I input. In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer. Can be floated if CW mode is not used. Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer to CLKM_1X G9 I Figure 88 for details). In the 1X clock mode, this pin is the quadrature-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used. Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the quadrature-phase 1X CLKP for CLKP_1X G8 I the CW mixer. Can be floated if CW mode is not used. Bias voltage and bypass to ground. ≥ 1 µF is recommended. To suppress the ultra low frequency noise, 10 µF CM_BYP B1 Bias can be used. Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be connected CW_IP_AMPINM E2 O between CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative output when PGA test mode is enabled. Can be floated if not used. Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be connected CW_IP_AMPINP E1 O between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be floated if not used. Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be connected CW_IP_OUTM F1 O between CW_IP_AMPINP andCW_IP_OUTPM. Can be floated if not used. Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be connected CW_IP_OUTP F2 O between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used. Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be CW_QP_AMPINM J2 O connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative output when PGA test mode is enabled. Can be floated if not used. Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be CW_QP_AMPINP J1 O connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive output when PGA test mode is enabled. Can be floated if not used. Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be CW_QP_OUTM H1 O connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used. Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be CW_QP_OUTP H2 O connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used. N8, P9~P7, D1M~D8M O ADC CH1~8 LVDS negative outputs P3~P1, N2 N9, R9~R7, D1P~D8P O ADC CH1~8 LVDS positive outputs R3~R1, N1 DCLKM P6 O LVDS bit clock (7x) negative output DCLKP R6 O LVDS bit clock (7x) positive output K7, DNC L5~L7,M5~ — Do not connect. Must leave floated. M8, N4, N6 DVDD N3, N7 Supply ADC digital and I/O power supply, 1.8 V DVSS N5, P5, R5 — ADC digital ground FCLKM P4 O LVDS frame clock (1X) negative output FCLKP R4 O LVDS frame clock (1X) positive output CH1~8 complimentary analog inputs. Bypass to ground with ≥ 0.015-µF capacitors. The HPF response of the INM1…INM8 C9~C2 I LNA depends on the capacitors. INP1...INP8 A9~A2 I CH1~8 analog inputs. AC couple to inputs with ≥ 0.1-µF capacitors. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: AFE5808A |
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