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5962R0722701V9A Datasheet(PDF) 9 Page - Texas Instruments |
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5962R0722701V9A Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 30 page  9 ADC128S102QML-SP www.ti.com SNAS411P – AUGUST 2008 – REVISED APRIL 2017 Product Folder Links: ADC128S102QML-SP Submit Documentation Feedback Copyright © 2008–2017, Texas Instruments Incorporated (1) This is worse case drift, Deltas are performed at room temperature post operational life. All other parameters, no deltas are required. 6.7 Electrical Characteristics: Burn in Delta Parameters - TA at 25°C The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INL Integral non-linearity VA = VD = 3 V –0.5 0.106 0.5 LSB VA = VD = 5 V –0.35 0.016 0.35 LSB IMD Intermodulation distortion, second order terms VA = VD = 3 V –14 1.35 14 dB VA = VD = 5 V –17 1.67 17 dB IMD Intermodulation distortion, third order terms VA = VD = 3 V –10 0.47 10 dB VA = VD = 5 V –10 0.9 10 dB (1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. (2) Clock may be in any state (high or low) when CS goes high. Setup and hold time restrictions apply only to CS going low. 6.8 Timing Requirements The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF. SUBGROUP MIN NOM(1) MAX UNIT tCSH CS hold time after SCLK rising edge See (2) [9, 10, 11] 10 0 ns tCSS CS setup time prior to SCLK rising edge See (2) [9, 10, 11] 10 4.5 ns tEN CS falling edge to DOUT enabled [9, 10, 11] 5 30 ns tDACC DOUT access time after SCLK falling edge [9, 10, 11] 17 27 ns tDHLD DOUT hold time after SCLK falling edge [9, 10, 11] 7 ns tDS DIN setup time prior to SCLK rising edge [9, 10, 11] 10 ns tDH DIN hold time after SCLK rising edge [9, 10, 11] 10 ns tCH SCLK high time 0.4 × tSCLK ns tCL SCLK low time 0.4 × tSCLK ns tDIS CS rising edge to DOUT high- impedance DOUT falling [9, 10, 11] 2.4 20 ns DOUT rising [9, 10, 11] 0.9 20 ns (1) MIL-STD-883, Method 5005 - Group A Table 1. Quality Conformance Inspection(1) SUBGROUP DESCRIPTION TEMP (°C) 1 Static tests at 25 2 Static tests at 125 3 Static tests at –55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at –55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at –55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at –55 12 Setting time at 25 13 Setting time at 125 14 Setting time at –55 |
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