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PE42420LGBB-Z Datasheet(PDF) 9 Page - Peregrine Semiconductor |
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PE42420LGBB-Z Datasheet(HTML) 9 Page - Peregrine Semiconductor |
9 / 12 page Product Specification PE42420 Page 9 of 12 Document No. DOC-78041-1 │ www.psemi.com ©2016 Peregrine Semiconductor Corp. All rights reserved. Evaluation Kit The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine’s PE42420. The RF common port is connected through a 50Ω transmission line via the top SMA connector, J2. RF1 and RF2 ports are connected through 50Ω transmission lines via SMA connectors J1 and J3, respectively. A 50Ω through transmission line is available via SMA connectors J4 and J5, which can be used to calculate the loss of the PCB. J6 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 36 mils. To achieve high isolation, the 50Ω transmission lines are designed in layer 2 using a stripline waveguide design. The board stack up for 50Ω transmission lines has 10 mil thickness of Rogers 4350 between layer 1 and layer 2, and 10 mil thickness of Rogers 4350 between layer 2 and layer 3. For the true performance of the PE42420 to be realized, the PCB should be designed in such a way that RF transmission lines and sensitive DC I/O traces are heavily isolated from one another. Figure 19. Evaluation Board Layout PRT-11505 |
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