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AK7735EQ Datasheet(PDF) 46 Page - Asahi Kasei Microsystems |
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AK7735EQ Datasheet(HTML) 46 Page - Asahi Kasei Microsystems |
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46 / 142 page  [AK7735] 016014707-E-00 2016/12 - 46 - ■ Audio Data Path Setting 1. Data Bus, In/Output Port The AK7735 has a 32-bit serial audio stereo data bus (Figure 17). Inputs and outputs of each internal block and all input/output pins of the AK7735 are connected to this serial audio data bus. The port that data is input to this serial audio data bus is defined as “input port” and the port that data is output from the audio data bus is defined as “output port”. Each port selects Clock Sync Domain and inputs (outputs) audio data that synchronized to the reference clock of the Clock Sync domain to the data bus (Figure 17). A stereo data on each port is defined as “data source”. All data sources are connected to the serial audio bus and a data source on any input port can be output to any output port. Data connection of the input port and the output port with the same sampling frequency via data bus is defined as “data path”. Input and output ports on the same data path should have the same Clock Sync Domain. If these ports have different Clock Sync Domains, reference clocks (BICKSDx, LRCKSDx) must be synchronized and the sampling frequency of LRCKSDx must be the same. However, phase synchronization of reference clocks is not necessary and frequencies of BICKSDx can be different. An SRC is necessary for data transmission between two ports that have clock sync domain with different sampling frequencies or asynchronous reference clocks. e.g.) Data Path Example (Figure 16) It is an example of outputting data from the DAC1 after converting fs=8kHz input data from the SDIN1 pin to fs=48kHz by SRC. Path 1 is defined from the SDIN1 pin to SRC1. Path2 is defined from SRC1 to DAC1. Set the same clock sync domain for data ports of the Path1 (SDIN1 input and SRC1 output ports), and for the data ports of the Path2 (SRC1 input port and DAC1), independently. Data Bus DAC1 SDOUT1～ 5 DACI1 SDIN1pin SDIN1 SDOUT1～ 5 : Input Port : Output Port SDIN1 SDIN1 SRC1 SDIN1 SRCO1 SDOUT1～ 5 SRCI1 PATH1(fs=8kHz) PATH2(fs=48kHz) Figure 16. Data Path Example |
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