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AK5558VN Datasheet(PDF) 20 Page - Asahi Kasei Microsystems |
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AK5558VN Datasheet(HTML) 20 Page - Asahi Kasei Microsystems |
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20 / 70 page  [AK5558] 015099850-E-00 2016/03 - 20 - (Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), C L= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Slave mode) Normal mode (TDM1- 0 bits = “00”) (8 kHz fs 216 kHz) (Figure 19) (LDOE pin = “H”) BICK Period Normal Speed mode Double Speed mode Quad Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) LRCK to SDTO (MSB) (Except I 2S mode) BICK “↓”to SDTO1/2/3/4 tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/128fsn 1/128fsd 1/64fsq 32 32 25 25 - - - - - - - - - - - - - - - - - - 25 25 ns ns ns ns ns ns ns ns ns Normal mode (TDM1-0 bits = “00”) (8 kHz ≤ fs ≤ 216 kHz) (Figure 19) (LDOE pin = “L”) BICK Period Normal Speed mode (8 kHz ≤ fs ≤ 48 kHz) Double Speed mode (48 kHz ≤ fs ≤ 96 kHz) Quad Speed mode (96 kHz ≤ fs ≤ 192 kHz) BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) LRCK to SDTO (MSB) (Except I 2S mode) BICK “↓” to SDTO1/2/3/4 tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/128fsn 1/128fsd 1/64fsq 36 36 30 30 - - - - - - - - - - - - - - - - - - 30 30 ns ns ns ns ns ns ns ns ns Normal mode (TDM1-0 bits = “00”) (fs = 384 kHz, 768 kHz) (Figure 20) BICK Period Oct Speed mode Hex Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1/2/3/4 tBCK tBCK tBCKL tBCKH tLRB tBLR tBSDD 1/64fso 1/48fsh 12 12 12 12 5 - - - - - - - - - - - - - 22 ns ns ns ns ns ns ns Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5558 should be reset by the PDN pin or RSTN bit. Note 19. BICK rising edge must not occur at the same time as LRCK edge. |
Similar Part No. - AK5558VN_16 |
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Similar Description - AK5558VN_16 |
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