AK4376AECB datasheet(9/68 Pages) AKM

Part #	AK4376AECB

Description	Low-Power Advanced 32-bit DAC with HP

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Manufacturer	AKM [Asahi Kasei Microsystems]

Direct Link	http://www.akm.com

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9 / 68 page

[AK4376A]

016014206-E-00

2016/11

- 9 -

6. Absolute Maximum Ratings

(VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 7, Note 8)

Parameter

Symbol

Min.

Max.

Unit

Power

Analog

AVDD

0.3

4.3

V

Supplies:

HP-Amp/Charge Pump

CVDD

0.3

4.3

V

(Note 6)

LDO2 for Digital Core

LVDD

0.3

4.3

V

Digital I/F

TVDD

0.3

4.3

V

Input Current, Any Pin Except Supplies

IIN

-

10

mA

Analog Input Voltage (Note 9)

VINA

0.3

AVDD+0.3 or 4.3

V

Digital Input Voltage (Note 10)

VIND

0.3

TVDD+0.3 or 4.3

V

Ambient Temperature (powered applied)

Ta

40

85

C

Storage Temperature

Tstg

65

150

C

Note 6. Charge pump 1 & 2 are not in operation. In the case that charge pump 1 & 2 are in operation, the

maximum values of AVDD and CVDD become 2.15 V.

Note 7. All voltages with respect to ground.

Note 8. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog plane.

Note 9. XTI pin

The maximum value of input voltage is lower value between (AVDD+0.3)V and 4.3V.

Note 10. MCKI, BCLK, LRCK, SDATA, SCL, SDA, PDN, TESTI1, TESTI2 pins

The maximum value of input voltage is lower value between (TVDD+0.3)V and 4.3V.

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal

Operation is not guranteed at these extremes.

7. Recommended Operating Conditions

(VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 11)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Power

Analog

AVDD

1.7

1.8

1.9

V

supplies

HP-Amp / Charge Pump

CVDD

1.7

1.8

1.9

V

(Note 12)

LDO2 for Digital Core

LVDD

1.7

1.8

1.9

V

Digital I/F

TVDD

1.65

1.8

3.6

V

Note 11. All voltages with respect to ground.

Note 12. Each power up/down sequence is shown below.

<Power-up>

1. PDN pin =

“L”

2. TVDD, AVDD, LVDD, CVDD

(AVDD must be powered up before or at the same time of CVDD. The power-up sequence of

TVDD and LVDD is not critical.)

3.

The PDN pin is allowed to be “H” after all power supplies are applied and settled.

<Power-down>

1. PDN pin =

“L”

2. TVDD, AVDD, LVDD, CVDD

(CVDD must be powered down before or at the same time of AVDD. The power-down

sequence of TVDD and LVDD is not critical.)

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