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LP2994M Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LP2994M Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 15 page Typical Application Circuits (Continued) DDR-II Applications With the separate V DDQ pin and an internal resistor divider it is possible to use the LP2994 in applications utilizing DDR-II memory. Figure 7 and Figure 8 show several implementa- tions of recommended circuits with output curves displayed in the Typical Performance Characteristics. Figure 7 shows the recommended circuit configuration for DDR-II applica- tions. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower V TT output voltages. For this reason, it is not recommended to power PVIN off a rail higher than the nominal 3.3V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current. If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times V DDQ for regulating the output voltage. Sev- eral options are available to scale the output to any voltage required. One method is to level shift the output by using feedback resistors from V TT to the VSENSE pin. This has been illustrated in Figure 9 and Figure 10. Figure 9 shows 20045906 FIGURE 6. SSTL-2 Implementation with higher voltage rails 20045907 FIGURE 7. Recommended DDR-II Termination 20045908 FIGURE 8. DDR-II Termination with higher voltage rails www.national.com 11 |
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