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C1005X5R1V105M050BC Datasheet(PDF) 9 Page - Vishay Siliconix |
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C1005X5R1V105M050BC Datasheet(HTML) 9 Page - Vishay Siliconix |
9 / 23 page SiC462 www.vishay.com Vishay Siliconix S17-0360-Rev. D, 13-Mar-17 9 Document Number: 65124 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Soft-Start SiC462 soft-start time is adjustable by selecting a capacitor value from the following equation. Once VCC is above UVLO level (2.55 V typ.), VOUT will ramp up slowly, rising monotonically to the programmed output voltage. There is an internal 5 μA current source tied to the soft start pin which charges the external soft start cap. During soft-start period, OCP is activated. Short-circuit protection is not active until soft-start is complete. Pre-Bias Start-Up In case of pre-bias startup, output is monitored through FB pin. If the sensed voltage on FB is higher than the internal reference ramp value, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. Fig. 7 - Pre-Bias Start-Up Fig. 8 - PGOOD Window and Timing Diagram Power Good SiC462’s power good is an open-drain output. Pull PGOOD pin high up to 5 V through a 10K resistor to use this signal. Power good window is shown in the diagram above. If voltage level on FB pin is out of this window, PG signal is de-asserted by pulling down to GND. To prevent false triggering during transient events, PGOOD has a 25 μs blanking time. SS time C ext x 0.8 V 5 μA -------------------------------- = Vref (0.8 V) VFB VFB_Rising_Vth_OV (typ. = 0.96 V) VFB_Falling_Vth_OV (typ. = 0.91 V) VFB_Falling_Vth_UV (typ. = 0.72 V) VFB_Rising_Vth_UV (typ. = 0.77 V) PG Pull-high Pull-low |
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