Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

IDT72V225L20PF Datasheet(PDF) 11 Page - Integrated Device Technology

Part # IDT72V225L20PF
Description  3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V225L20PF Datasheet(HTML) 11 Page - Integrated Device Technology

Back Button IDT72V225L20PF Datasheet HTML 7Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 8Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 9Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 10Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 11Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 12Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 13Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 14Page - Integrated Device Technology IDT72V225L20PF Datasheet HTML 15Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 25 page
background image
11
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then
FF may not change state until the next WCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 5. Reset Timing(2)
Figure 6. Write Cycle Timing with Single Register-Buffered
FF (IDT Standard Mode)
WCLK
D0 - D17
WEN
FF
tCLK
tCLKH
tCLKL
tDS
tENS
tDH
tENH
tWFF
tWFF
DATA IN VALID
NO OPERATION
RCLK
tSKEW1
(1)
REN
4294 drw 06
RS
REN, WEN, LD
PAE
PAF, WXO/
HF, RXO
Q0 - Q17
OE = 0
OE = 1
(1)
4294 drw 05
tRSS
CONFIGURATION SETTING
tRSR
FL, RXI, WXI
RCLK, WCLK
FF/IR
EF/OR
FWFT Mode
IDT Standard Mode
(3)
(2)
tRSF
tRSF
tRSF
tRSF
tRSF
tRSR
tRS
FWFT Mode
IDT Standard Mode
(4)
NOTES:
1. Single device mode (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if
OE = 0 and tri-state if OE = 1.
4. In FWFT mode
IR goes LOW based on the WCLK edge after Reset.


Similar Part No. - IDT72V225L20PF

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT72V225 IDT-IDT72V225 Datasheet
401Kb / 25P
   3.3 VOLT CMOS SyncFIFO
logo
Renesas Technology Corp
IDT72V225 RENESAS-IDT72V225 Datasheet
380Kb / 26P
   3.3 VOLT CMOS SyncFIFOTM
MARCH 2018
More results

Similar Description - IDT72V225L20PF

ManufacturerPart #DatasheetDescription
logo
Renesas Technology Corp
IDT72V805 RENESAS-IDT72V805 Datasheet
399Kb / 27P
   3.3 VOLT CMOS DUAL SyncFIFO™ DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18
MARCH 2018
logo
Integrated Device Techn...
IDT72805LB IDT-IDT72805LB Datasheet
334Kb / 26P
   CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
IDT72V805 IDT-IDT72V805 Datasheet
490Kb / 26P
   3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18
IDT72205LB IDT-IDT72205LB Datasheet
181Kb / 16P
   CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72605 IDT-IDT72605 Datasheet
209Kb / 20P
   CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2
IDT72V201 IDT-IDT72V201 Datasheet
115Kb / 14P
   3.3 VOLT CMOS SyncFIFO??256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
IDT72V255LA IDT-IDT72V255LA Datasheet
439Kb / 27P
   3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18
logo
Sharp Corporation
LH540215 SHARP-LH540215 Datasheet
423Kb / 48P
   512 x 18 / 1024 x 18 Synchronous FIFO
logo
Renesas Technology Corp
72V275 RENESAS-72V275 Datasheet
553Kb / 26P
   3.3 VOLT CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18
FEBRUARY 2018
72V255LA RENESAS-72V255LA Datasheet
402Kb / 28P
   3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18
JANUARY 2018
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com