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FS612509-01 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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FS612509-01 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 8 page AMERICAN MICROSYSTEMS, INC. November 2000 ISO9001 ISO9001 ISO9001 ISO9001 QS9000 QS9000 QS9000 QS9000 6 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC Table 7: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Skew, Output to Output * tsk(o) Measured on the rising edge at 1.65V; CL = 15pF 150 ps Skew, Tracking * Measured using a –0.5% 31.5kHz spread spectrum reference clock at 133.33MHz 150 ps Static Phase Error * From rising edge on CLK to rising edge on FBIN -120 ps Clock Stabilization Time * Time required for the PLL to achieve phase lock 3 ms Loop Bandwidth * For calculation of Tracking Skew 1.2 MHz Phase Angle * For calculation of Tracking Skew -0.031 ° Clock Outputs (1Y0:4, 2Y0:3, FBOUT) Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.65V 45 55 % Jitter, Cycle-Cycle * tj(CC) Adjacent cycles at 1.65V -75 +75 ps Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at 1.65V Rise Time * tr VO = 0.4V to 2.0V; CL = 15pF 1.2 ns Fall Time * tf VO = 2.0V to 0.4V; CL = 15pF 1.4 ns Enable Delay * tDLH via 1G or 2G 1 10 ns Disable Delay * tDHL via 1G or 2G 1 10 ns Figure 3: Clock Skew Measurement clock skew (t sk(o)) Any output Any output 50% V DD 50% V DD Figure 4: Phase Error Measurement phase error CLK FBIN 50% V DD 50% V DD Figure 5: Timing Measurement Points 0.4V 2.4V 3.3V d t t f t r 50% V DD Figure 6: Output Enable Measurement t DLZ V OL V OH V SS V DD 10% 90% t DHZ 50% 50% 50% 50% t DZL t DHZ Output Enable Output |
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