XR21B1411

7

REV. 1.2.0

ENHANCED 1-CH FULL-SPEED USB UART

1st byte

2nd byte

9 bit m ode

7

6

5

4

3

2

1

0

x

x

x

x

O F B P

1st byte

B = Break

F = Fram ing Error

O = O verrun Error

2nd byte

7 or 8 bit m ode

P = Parity Error (= ‘0’ if not enabled)

7 = ‘0’ in 7 bit m ode

x = ‘0’

7

6

5

4

3

2

1

0

x

x

x

x

O F B 8B = Break

F = Fram ing Error

O = O verrun Error

x = ‘0’

Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags

are historical flags indicating that an error has occurred since the previous request. Therefore, no conclusion

can be drawn as to which specific byte(s) may have contained an actual error in this manner.

1.3.3

Rx FIFO Low Latency

In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to

minimize host processing. When there are 64 bytes of data in the RX FIFO, the B1411 will acknowledge a

bulk-in request from the host and transfer the data packet. If there is less than 64 bytes in the RX FIFO, the

B1411 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if there

is less than 64 bytes in the RX FIFO and no data has been received for more than 3 character times, the B1411

will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.

In some cases, especially when the baud rate is low, this increases latency unacceptably. The B1411 has a

low latency register bit that will cause the B1411 to immediately transfer any received data in the RX FIFO to

the USB host, i.e. it will not wait for 3 character times. The custom driver can automatically set the

RX_FIFO_LOW_LATENCY register bit to force the B1411 to be in the low latency mode, or the user may

manually set this bit. With the CDC-ACM driver, the low latency mode is automatically set whenever the baud

rate is set to a value of less than 40961 bps using the CDC_ACM_IF_SET_LINE_CODING command.

1.3.4

GPIO

The UART has 6 GPIOs. By hardware default the GPIOs are configured as inputs but may be modified by a

custom driver. However, they can also be configured to add additional features such as Auto RTS/CTS Flow

control, Auto DTR/DSR Flow Control or auto RS-485 half duplex control. Both GPIO modes 3 and 4 may be

used to automatically assert GPIO5 as auto RS-485 half duplex control. See Table 7 for the register control

and details of GPIO modes. Note that settings in the GPIO mode register should coordinate with settings in

the Flow Control mode register described in “Section 1.3.5, Flow Control” on page 7. Not all combinations

of these two registers will be valid. See “Section 1.3.7, Multidrop mode with address matching” on page 9

for more details regarding Rx address matching.

1.3.5

Flow Control

The B1411 can perform both hardware and software flow control. Software flow control is selected by flow

control mode 2. Hardware flow control can either be RTS/CTS or DTR/DSR controlled and is selected by flow

control mode 1. See Table 6 for the register control and details of flow control modes. The following sections

describe the three types of flow control which may be used.