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XR20M1170IG16TR-F Datasheet(PDF) 10 Page - Exar Corporation |
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XR20M1170IG16TR-F Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 56 page  FIGURE 10. SPI FIFO READ SCLK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 last bit R/W A3 A2 A1 A0 0 0X XR20M1170 10 I2C/SPI UART WITH 64-BYTE FIFO REV. 1.1.0 After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW). 2.2 Device Reset The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state (see Table 16). An active low pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.3 Internal Registers The M1170 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to the industry standard ST16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register (SPR). Beyond the general 16C550 features and capabilities, the M1170 offers enhanced feature registers (EFR, Xon/ Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, automatic RS-485 half- duplex direction output enable/disable, TX and RX FIFO level counters, and programmable FIFO trigger level control. For complete details, see “Section 3.0, UART Internal Registers” on page 23. 2.4 IRQ# Output The IRQ# interrupt output changes according to the operating mode and enhanced features setup. Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 21 through 35. TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER Auto RS485 Mode FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) IRQ# Pin NO HIGH = a byte in THR LOW = THR empty HIGH = FIFO above trigger level LOW = FIFO below trigger level or FIFO empty IRQ# Pin YES HIGH = a byte in THR LOW = transmitter empty HIGH = FIFO above trigger level LOW = FIFO below trigger level or transmitter empty TABLE 5: IRQ# PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) IRQ# Pin HIGH = no data LOW = 1 byte HIGH = FIFO below trigger level LOW = FIFO above trigger level |
Similar Part No. - XR20M1170IG16TR-F |
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Similar Description - XR20M1170IG16TR-F |
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