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XR20M1172IL32TR-F Datasheet(PDF) 10 Page - Exar Corporation |
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XR20M1172IL32TR-F Datasheet(HTML) 10 Page - Exar Corporation |
10 / 55 page XR20M1172 10 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO REV. 1.2.0 2.1.2 SPI Bus Interface The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input (SI). The serial clock, slave output and slave input can be as fast as 18 MHz at 3.3V. To access the device in the SPI mode, the CS# signal for the M1172 is asserted by the SPI master, then the SPI master starts toggling the SCL signal with the appropriate transaction information. The first bit sent by the SPI master includes whether it is a read or write transaction and the UART register being accessed. See Table 3 below. TABLE 3: SPI FIRST BYTE FORMAT BIT FUNCTION 7 Read/Write# Logic 1 = Read Logic 0 = Write 6:3 UART Internal Register Address A3:A0 2:1 UART Channel Select ’00’ = UART Channel A ’01’ = UART Channel B Other values are reserved 0 Reserved FIGURE 7. SPI WRITE FIGURE 8. SPI READ R /W A 3 A 2 A 1 A 0 0 C H X D 7 D6 D 5 D4 D 3 D2 D 1 D0 S C LK SI R /W A 3 A 2 A 1 A 0 0 C H X D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S C LK S I S O |
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