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XR17V352IB113-F Datasheet(PDF) 8 Page - Exar Corporation |
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XR17V352IB113-F Datasheet(HTML) 8 Page - Exar Corporation |
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8 / 64 page  XR17V352 8 HIGH PERFORMANCE DUAL PCI EXPRESS UART REV. 1.0.4 FUNCTIONAL DESCRIPTION The XR17V352 (V352) integrates the functions of two independent enhanced 16550 UARTs, a general purpose 16-bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550 UART compatible configuration register set for individual channel control, status and data transfer. The device configuration registers include a set of four consecutive interrupt source registers that provides interrupt status for both UARTs, timer/counter, MPIOs and a sleep wake-up indicator. Additionally, each UART channel has 256-byte of transmit and receive FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control, automatic XON/XOFF, special character flow control, programmable transmit and receive FIFO trigger levels, infrared encoder/decoder (IrDA ver. 1.1), and a programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and a data rate up to 31.25 Mbps with the 4X sampling rate. PCI LOCAL BUS CONFIGURATION SPACE REGISTERS A set of local bus configuration space register is provided. These registers provide the PCI vendor ID, device ID, sub-vendor ID, product model number, resources and capabilities which is collected by the host during the auto configuration phase that follows immediately after a power up or system reset/reboot. After the host has sorted out all devices on the bus, it defines and download the operating conditions to the cards. One of the definitions is the base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI local bus memory space. All this is described in more detail in “Section 1.1, PCI LOCAL BUS CONFIGURATION SPACE REGISTERS” on page 9. EEPROM INTERFACE An external 93C46 EEPROM is used to store words of information such as PCI Vendor ID, PCI Device ID, Class Code, etc. Details of this information can be found in “Section 1.2, EEPROM Interface” on page 13. This information is only used with the plug-and-play auto configuration of the PCI local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface consists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is not required in the application. However, if your design requires non-volatile memory for other purpose, it is possible to store and retrieve data on the EEPROM through a special PCI device configuration register. See application note DAN112 for its programming details. BUCK REGULATOR The on chip buck regulator provides a 1.2V output from the device when enabled. This voltage can in turn be used to provide power to the digital core and analog Phy as depicted in Figure 3. LX LX A9 A10 FB ENABLE PWRGD VCC12 VCC12 47 uF (Tantalum) 4.7 uH VCC12A H2 C10 4.7 k C7 D9 475 O Ferrite Bead VCC12 VCC12 VCC12 VCC12 D7 G8 H5 Ferrite Bead FIGURE 3. BUCK REGULATOR |
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