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COP445C Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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COP445C Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 24 page  Functional Description The internal architecture is shown in Figure 1 Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implement- ing the instruction set of the device Positive logic is used When a bit is set it is a logic ‘‘1’’ when a bit is reset it is a logic ‘‘0’’ For ease of reading only the COP424C425CCOP426C 444C445C are referenced however all such references apply equally to COP324C325CCOP326C344C345C PROGRAM MEMORY Program Memory consists of ROM 1024 bytes for the COP424C425C426C and 2048 bytes for the COP444C 445C These bytes of ROM may be program instructions constants or ROM addressing data ROM addressing is accomplished by a 11-bit PC register which selects one of the 8-bit words contained in ROM A new address is loaded into the PC register during each in- struction cycle Unless the instruction is a transfer of control instruction the PC register is loaded with the next sequen- tial 11-bit binary count value Three levels of subroutine nesting are implemented by a three level deep stack Each subroutine call or interrupt pushes the next PC address into the stack Each return pops the stack back into the PC register DATA MEMORY Data memory consists of a 512-bit RAM for the COP444C 445C organized as 8 data registers of 16 c 4-bit digits RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register Data memory consists of a 256-bit RAM for the COP424C 425C426C organized as 4 data registers of 16 c 4-bits digits The B register is 6 bits long Upper 2 bits (Br) select 1 of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from or exchanged with the A register (accumulator) it may also be loaded into or from the Q latches or T counter or loaded from the L ports RAM addressing may also be performed directly by the LDD and XAD instructions based upon the immediate operand field of these instructions The Bd register also serves as a source register for 4-bit data sent directly to the D outputs INTERNAL LOGIC The processor contains its own 4-bit A register (accumula- tor) which is the source and destination register for most IO arithmetic logic and data memory access operations It can also be used to load the Br and Bd portions of the B regis- ter to load and input 4 bits of the 8-bit Q latch or T counter to input 4 bits of L IO ports data to input 4-bit G or IN ports and to perform data exchanges with the SIO register A 4-bit adder performs the arithmetic and logic functions storing the results in A It also outputs a carry bit to the 1-bit C register most often employed to indicate arithmetic over- flow The C register in conjunction with the XAS instruction and the EN register also serves to control the SK output The 8-bit T counter is a binary up counter which can be loaded to and from M and A using CAMT and CTMA instruc- tions When the T counter overflows an overflow flag will be set (see SKT and IT instructions below) The T counter is cleared on reset A functional block diagram of the timer counter is illustrated in Figure 10a Four general-purpose inputs IN3-IN0 are provided IN1 IN2 and IN3 may be selected by a mask-programmable op- tion as Read Strobe Chip Select and Write Strobe inputs respectively for use in Microbus application The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd In the dual clock mode D0 latch controls the clock selection (see dual oscillator below) The G register contents are outputs to a 4-bit general-pur- pose bidirectional IO port G0 may be mask-programmed as an output for Microbus applications The Q register is an internal latched 8-bit register used to hold data loaded to or from M and A as well as 8-bit data from ROM Its contents are outputted to the L IO ports when the L drivers are enabled under program control With the Microbus option selected Q can also be loaded with the 8-bit contents of the L IO ports upon the occurrence of a write strobe from the host CPU The 8 L drivers when enabled output the contents of latched Q data to the L IO port Also the contents of L may be read directly into A and M As explained above the Microbus option allows L IO port data to be latched into the Q register 7 |
Similar Part No. - COP445C |
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Similar Description - COP445C |
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