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COP325C Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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COP325C Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 24 page  Functional Description (Continued) INITIALIZATION The internal reset logic will initialize the device upon power- up if the power supply rise time is less than 1 ms and if the operating frequency at CKI is greater than 32 kHz other- wise the external RC network shown in Figure 7 must be connected to the RESET pin (the conditions in Figure 7 must be met) The RESET pin is configured as a Schmitt trigger input If not used it should be connected to VCC Initialization will occur whenever a logic ‘‘0’’ is applied to the RESET input providing it stays low for at least three instruc- tion cycle times Note If CKI clock is less than 32 kHz the internal reset logic (option 29e1) MUST be disabled and the external RC circuit must be used TLDD5259 – 8 FIGURE 7 Power-Up Circuit Upon initialization the PC register is cleared to 0 (ROM ad- dress 0) and the A B C D EN IL T and G registers are cleared The SKL latch is set thus enabling SK as a clock output Data Memory (RAM) is not cleared upon initializa- tion The first instruction at address 0 must be a CLRA (clear A register) TIMER The timer can be operated as a time-base counter The instruction cycle frequency generated from CKI passes through a 2-bit divide-by-4 prescaler The output of this pre- scaler increments the 8-bit T counter thus providing a 10-bit timer The pre-scaler is cleared during execution of a CAMT instruction and on reset For example using a 4 MHz crystal with a divide-by-16 op- tion the instruction cycle frequency of 250 kHz increments the 10-bit timer every 4 ms By presetting the counter and detecting overflow accurate timeouts between 16 ms (4 counts) and 4096 ms (1024 counts) are possible Longer timeouts can be achieved by accumulating under software control multiple overflows HALT MODE The COP444C445C424C425C426C is a FULLY STAT- IC circuit therefore the user may stop the system oscillator at any time to halt the chip The chip may also be halted by the HALT instruction or by forcing CKO high when it is mask-programmed as an HALT IO port Once in the HALT mode the internal circuitry does not receive any clock sig- nal and is therefore frozen in the exact state it was in when halted All information is retained until continuing The chip may be awakened by one of two different methods Continue function by forcing CKO low if it mask-pro- grammed as an HALT IO port the system clock is re- enabled and the circuit continues to operate from the point where it was stopped Restart by forcing the RESET pin low (see Initializa- tion) TLDD5259 – 9 Crystal or Resonator Crystal Component Values Value R1 R2 C1(pF) C2(pF) 32 kHz 220k 20M 30 6 – 36 455 kHz 5k 10M 80 40 2096 MHz 2k 1M 30 6 – 36 40 MHz 1k 1M 30 6 – 36 RC Controlled Oscillator (g5% R g5% C) RC Cycle VCC Time 30k 82 pF 5 – 11 ms t 45V 60k 100 pF 12 – 24 ms 24 – 45V Note 15ksRs150k 50 pFsCs150 pF FIGURE 8 Oscillator Component Values 10 |
Similar Part No. - COP325C |
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Similar Description - COP325C |
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